From 854848c39d83ff3e3c9812a45701cb1eb3a11254 Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Tue, 6 Oct 2020 16:52:32 +0800 Subject: mb/google/volteer/var/voxel: disable DdiPortHpd GPP_A19 and GPP_A20 set no connection, disables DdiPort1Hpd and DdiPort2Hpd BUG=b:169690329 TEST=build and verify type-c(C0/C1) port functional normally Signed-off-by: Pan Sheng-Liang Change-Id: I4405526ae777332d3c72041db7b4eda25ae31b8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46069 Reviewed-by: Tim Wawrzynczak Reviewed-by: TH Lin Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/variants/voxel/overridetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/google/volteer/variants/voxel') diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 8ce687567b..d7a265b010 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,4 +1,6 @@ chip soc/intel/tigerlake + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" register "tcc_offset" = "5" # TCC of 95 register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ -- cgit v1.2.3