diff options
| author | Felix Singer <felixsinger@posteo.net> | 2021-07-11 02:48:06 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-07-17 00:10:21 +0000 |
| commit | f7100eb1c9b6da9a3f8684e543e0a52246a7adfc (patch) | |
| tree | 3d2d82f62916cd1d4821a8fcbd9323af06e88b09 /src/mainboard/google/volteer/variants/volteer2/overridetree.cb | |
| parent | 5f235b0a3f3d12abd3556d593b352babe022ce32 (diff) | |
mb/google/volteer: Deduplicate lockdown config
The setting `chipset_lockdown` has the same configuration for all
variants and they also match with the baseboard configuration. Thus,
remove it from the variant overridetrees.
Built google/delbin with `BUILD_TIMELESS=1` and coreboot.rom
remains the same.
Change-Id: I597e4487e7a0e1848d2a2f2c8f8ebd552994aac2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56199
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/volteer/variants/volteer2/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/volteer/variants/volteer2/overridetree.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 44a753f56f..8fc4d7b4a9 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -6,7 +6,6 @@ chip soc/intel/tigerlake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI0 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -21,7 +20,6 @@ chip soc/intel/tigerlake # Depending on whether we use I2C bus 1 or SPI bus 0 for TPM # communication, that one needs early initialization. register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[0] = { .speed_mhz = 1, .early_init = CONFIG(MAINBOARD_HAS_SPI_TPM_CR50), |