diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-27 22:58:52 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-29 20:03:50 +0000 |
| commit | bc8f5405b542eef35a71e5189d71654cbe134558 (patch) | |
| tree | 289b1339565fb614281b31e07f09bb933c1465b8 /src/mainboard/google/volteer/variants/lindar/overridetree.cb | |
| parent | 0adf35537bd6093b79b1701becee823d3436d975 (diff) | |
tgl mainboards: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: Ide5126c6e642ca16249efeaf46321724f2ddce9a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/mainboard/google/volteer/variants/lindar/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/volteer/variants/lindar/overridetree.cb | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index b74bb238cd..2229af7d1d 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -4,15 +4,6 @@ chip soc/intel/tigerlake register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" - # USB Port Config - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C C1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C C0 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 - #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ @@ -327,6 +318,16 @@ chip soc/intel/tigerlake end end device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), // Type-A Port A0 + [3] = USB2_PORT_TYPE_C(OC_SKIP), // Type-A / Type-C C1 + [4] = USB2_PORT_MID(OC_SKIP), // M.2 Camera + [8] = USB2_PORT_TYPE_C(OC_SKIP), // Type-A / Type-C C0 + [9] = USB2_PORT_MID(OC_SKIP), // M.2 Bluetooth + }" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 + chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi |