mb, soc/intel: Reorganize CNVi device entries in devicetree

This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.

Before:
chip drivers/wifi/generic
	register "wake" = "..."
	device pci xx.y on end
end

After:
device pci xx.y on
	chip drivers/wifi/generic
		register "wake" = "..."
		device generic 0 on end
	end
end

Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

1 files changed, 5 insertions, 3 deletions

diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 2a62505757..bbec04b18b 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -433,9 +433,11 @@ chip soc/intel/tigerlake
 		device ref cnvi_bt on end
 		device ref south_xhci on end
 		device ref shared_ram on end
-		chip drivers/wifi/generic
-			register "wake" = "GPE0_PME_B0"
-			device ref cnvi_wifi on end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
 		end
 		device ref heci1 on end
 		device ref sata on end