diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-28 06:28:43 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-07-05 20:55:19 +0000 |
| commit | 9b31a90e7fda68ad1b03b65fc295fad9a6a3986f (patch) | |
| tree | f72076897adbcea0a11db50d240b2bdc6d69bba8 /src/mainboard/google/volteer/variants/baseboard/devicetree.cb | |
| parent | d9cb2c12d7f6fde26b736fe5fe1ca3f5142b1f18 (diff) | |
tgl mainboards: Move PCIe root port settings into their device scope
Change-Id: I110cc95d536cb0fd3b5db85b84cca7a96e31401c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83253
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/volteer/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 4775b0fac5..5dfc69c271 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -93,29 +93,6 @@ chip soc/intel/tigerlake register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)" register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)" - # NVMe PCIE 9 using clk 0 - register "PcieRpLtrEnable[8]" = "1" - register "PcieClkSrcUsage[0]" = "8" - register "PcieClkSrcClkReq[0]" = "0" - register "PcieRpSlotImplemented[8]" = "1" - - # Optane PCIE 11 using clk 0 - register "PcieRpLtrEnable[10]" = "1" - register "HybridStorageMode" = "0" - register "PcieRpSlotImplemented[10]" = "1" - - # SD Card PCIE 8 using clk 3 - register "PcieRpLtrEnable[7]" = "1" - register "PcieRpHotPlug[7]" = "1" - register "PcieClkSrcUsage[3]" = "7" - register "PcieClkSrcClkReq[3]" = "3" - - # WLAN PCIE 7 using clk 1 - register "PcieRpLtrEnable[6]" = "1" - register "PcieClkSrcUsage[1]" = "6" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieRpSlotImplemented[6]" = "1" - # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" @@ -450,8 +427,20 @@ chip soc/intel/tigerlake register "SataPortsDevSlp[1]" = "1" register "SataPortsEnableDitoConfig[1]" = "1" end - device ref pcie_rp7 on end + device ref pcie_rp7 on + # WLAN PCIE 7 using clk 1 + register "PcieRpLtrEnable[6]" = "1" + register "PcieClkSrcUsage[1]" = "6" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieRpSlotImplemented[6]" = "1" + end device ref pcie_rp8 on + # SD Card PCIE 8 using clk 3 + register "PcieRpLtrEnable[7]" = "1" + register "PcieRpHotPlug[7]" = "1" + register "PcieClkSrcUsage[3]" = "7" + register "PcieClkSrcClkReq[3]" = "3" + probe DB_SD SD_GL9755S probe DB_SD SD_RTS5261 probe DB_SD SD_RTS5227S @@ -477,8 +466,19 @@ chip soc/intel/tigerlake end end end - device ref pcie_rp9 on end - device ref pcie_rp11 on end + device ref pcie_rp9 on + # NVMe PCIE 9 using clk 0 + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[0]" = "8" + register "PcieClkSrcClkReq[0]" = "0" + register "PcieRpSlotImplemented[8]" = "1" + end + device ref pcie_rp11 on + # Optane PCIE 11 using clk 0 + register "PcieRpLtrEnable[10]" = "1" + register "HybridStorageMode" = "0" + register "PcieRpSlotImplemented[10]" = "1" + end device ref uart0 on end device ref gspi0 on chip drivers/spi/acpi |