mb/google/volteer: add volteer mainboard initial support

Created a new Google baseboard named volteer from scratch.

BUG=b:142961277
BRANCH=master
TEST="emerge-volteer coreboot" compiles successfully.

Change-Id: I03a13f3df4e819ab9cf63ad69867c807d2a1b651
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 53 insertions, 0 deletions

diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl
new file mode 100644
index 0000000000..489d2f0222
--- /dev/null
+++ b/src/mainboard/google/volteer/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <arch/acpi.h>
+#include "variant/ec.h"
+#include "variant/gpio.h"
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	// Some generic macros
+	#include <soc/intel/tigerlake/acpi/platform.asl>
+
+	// global NVS and variables
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	// CPU
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+			#include <soc/intel/tigerlake/acpi/southbridge.asl>
+		}
+	}
+
+	// Chrome OS specific
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+	// Chrome OS Embedded Controller
+	Scope (\_SB.PCI0.LPCB)
+	{
+		// ACPI code for EC SuperIO functions
+		#include <ec/google/chromeec/acpi/superio.asl>
+		// ACPI code for EC functions
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
+
+	// Chipset specific sleep states
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}