diff options
| author | Kevin Paul Herbert <kevin@trippers.org> | 2016-08-04 14:35:30 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-08-11 15:16:40 +0200 |
| commit | d7127b09ae6ccd86f45d9c19cac3cb74d980af54 (patch) | |
| tree | e99e277cae8c216ca305cd6c28acdde902337b4b /src/mainboard/google/veyron_rialto/chromeos.c | |
| parent | bb003c8126f7b6de3651661535e9400ab4e9117b (diff) | |
fsp_Broadwell_DE: Do not set IRQ3 and IRQ4 to level
When booting Linux as a coreboot payload, serial access does not work
properly. This is because the setup code erroneously sets IRQ3 and
IRQ4 to level. The UART on Broadwell is 8250/16550 compatible, thus
ISA and edge-triggered.
This change is not necessary on the non-FSP version of Broadwell support.
The non-FSP version does not set these IRQ overrides.
Fix verified booting Linux 4.6.0-rc2 on Intel Camelback Mountain CRB,
using Intel FSP 1.0.
Change-Id: I17b466676e7f4891c3e75ce6208e1580c9eaf742
Signed-off-by: Kevin Paul Herbert <kevin@trippers.org>
Reviewed-on: https://review.coreboot.org/16065
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/veyron_rialto/chromeos.c')
0 files changed, 0 insertions, 0 deletions