diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2018-05-14 12:12:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-05-31 15:25:00 +0000 |
| commit | 405eb44fdb3a8a2d0188e2550367c846a76919aa (patch) | |
| tree | a5fb9f4f3892e67e45c1541a2af6d306356d8bc4 /src/mainboard/google/veyron_rialto/chromeos.c | |
| parent | 9593e973fa0e3a104837d1df9659b3992d915b34 (diff) | |
mb/google/poppy/variants/nocturne: configure the FPMCU interface
The FPMCU is using the standard cros-ec-spi interface on GSPI1.
Configure the GPIOs controlling the MCU too.
We need to be able to wake from S3 on the MCU interrupt, re-configure
GPE0 DW0 to point to GPP_C bank.
BRANCH=poppy
BUG=b:79666174
TEST=exercise the cros_ec interface, e.g. 'ectool --name=cros_fp version',
verify the MKBP events by doing 'ectool --name=cros_fp fpmode fingerup'
then 'ectool --name=cros_fp waitevent 5 10000', toggle the other GPIOs
with the flash_fp_mcu script.
Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/26684
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/veyron_rialto/chromeos.c')
0 files changed, 0 insertions, 0 deletions