diff options
| author | David Hendricks <dhendrix@chromium.org> | 2014-12-19 16:44:31 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-15 16:42:52 +0200 |
| commit | 2646573a0bdbc5b8447d8dfaf467eaead967eb4b (patch) | |
| tree | c21c2d11f2e9a643dc5967738adfbf4cc75566c8 /src/mainboard/google/veyron_brain/bootblock.c | |
| parent | 16e32ed2f317c410382ed3c4a37380d4e82cf9bb (diff) | |
Brain: Apply differences between Jerry and Brain
This applies the differences between Jerry and Brain:
- No EC
- No SD card
- Minor changes to GPIOs (no lid, power button active low)
- No variations between board IDs (yet)
- No backlight/display attached, but we do have some HDMI
and VOP configuration (need to double check that it's right).
BUG=none
BRANCH=none
TEST=built and booted on Brain (requires follow-up CL
to get into depthcharge)
Change-Id: Idbbc19856e05a145637c28d87c3e19855d13f03b
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 67151129c28ca7dd83464e5a5c183d006299293c
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I3c761d3d4d186a6208a772c05193bdcbd4a5c105
Original-Reviewed-on: https://chromium-review.googlesource.com/235921
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9638
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/mainboard/google/veyron_brain/bootblock.c')
| -rw-r--r-- | src/mainboard/google/veyron_brain/bootblock.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/mainboard/google/veyron_brain/bootblock.c b/src/mainboard/google/veyron_brain/bootblock.c index 5571d456f8..af353f89fa 100644 --- a/src/mainboard/google/veyron_brain/bootblock.c +++ b/src/mainboard/google/veyron_brain/bootblock.c @@ -45,6 +45,8 @@ void bootblock_mainboard_early_init() void bootblock_mainboard_init(void) { + gpio_output(GPIO(7, A, 0), 1); /* Power LED */ + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); @@ -71,9 +73,5 @@ void bootblock_mainboard_init(void) writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz); - /* spi0 for chrome ec */ - writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); - rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz); - setup_chromeos_gpios(); } |