diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2017-10-06 12:22:18 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-09 18:44:11 +0000 |
| commit | e9d8959c4f11399c7ec1609ecff204c8f3c9b3ea (patch) | |
| tree | 1b3ce3b45789ab204acda5853c6124bbc67c7046 /src/mainboard/google/veyron | |
| parent | 22579596ffa77889062d7655a366682cfeae84f7 (diff) | |
mainboard/intel/cannonlake_rvp: enable NVMe SSD
Turn on PCIe express port 9 of PCIe controller 3,
to enable NVMe SSD via M.2 socket 3 on RVP board.
TEST=Boot to OS using Intel NVMe SSD Pro 6
Change-Id: I2fd1cdcf2d9718bf2042262b0c9813811a706b4a
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21908
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/veyron')
0 files changed, 0 insertions, 0 deletions