veyron: Rename "veyron" board to "veyron_pinky"

We retroactively decided to use the variant name "pinky" for the Rk3288
board we're currently bringing up, and retcon the unadorned "veyron"
name to refer to the Rockchip evaluation board. Since we currently have
no interest to maintain coreboot support for that board in our tree,
let's rename everything to "veyron_pinky" and forget about "veyron".

CQ-DEPEND=CL:217592
BUG=chrome-os-partner:30167
TEST='emerge-veyron libpayload coreboot' fails but
'emerge-veyron_pinky libpayload coreboot' succeeds.

Change-Id: I88bf5cc2da7c2f969ea184b5f12affaa94045a06
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aa8ec24b63d11798fec1993091b113a0c0938c7a
Original-Change-Id: I366391efc8e0a7c610584b50cea331a0164da6f3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217674
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8869
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 0 insertions, 77 deletions

diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 409a7cad35..0000000000
--- a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
-	{
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		},
-		{
-			.rank = 0x1,
-			.col = 0xA,
-			.bk = 0x3,
-			.bw = 0x2,
-			.dbw = 0x1,
-			.row_3_4 = 0x0,
-			.cs0_row = 0xF,
-			.cs1_row = 0xF
-		}
-	},
-	{
-		.togcnt1u = 0x215,
-		.tinit = 0xC8,
-		.trsth = 0x1F4,
-		.togcnt100n = 0x35,
-		.trefi = 0x4E,
-		.tmrd = 0x4,
-		.trfc = 0xBB,
-		.trp = 0x8,
-		.trtw = 0x4,
-		.tal = 0x0,
-		.tcl = 0x8,
-		.tcwl = 0x6,
-		.tras = 0x14,
-		.trc = 0x1D,
-		.trcd = 0x8,
-		.trrd = 0x6,
-		.trtp = 0x4,
-		.twr = 0x8,
-		.twtr = 0x4,
-		.texsr = 0x200,
-		.txp = 0x4,
-		.txpdll = 0xD,
-		.tzqcs = 0x40,
-		.tzqcsi = 0x0,
-		.tdqs = 0x1,
-		.tcksre = 0x6,
-		.tcksrx = 0x6,
-		.tcke = 0x4,
-		.tmod = 0xC,
-		.trstl = 0x36,
-		.tzqcl = 0x100,
-		.tmrr = 0x0,
-		.tckesr = 0x5,
-		.tdpd = 0x0
-	},
-	{
-		.dtpr0 = 0x3AD48890,
-		.dtpr1 = 0xBB08D8,
-		.dtpr2 = 0x1002B600,
-		.mr[0] = 0x840,
-		.mr[1] = 0x40,
-		.mr[2] = 0x8,
-		.mr[3] = 0x0
-	},
-	.noc_timing = 0x2891E41D,
-	.noc_activate = 0x5B6,
-	.ddrconfig = 3,
-	.ddr_freq = 533000000,
-	.dramtype = DDR3,
-	.num_channels = 2,
-	.stride = 9,
-	.odt = 1
-},