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authorFelix Held <felix-coreboot@felixheld.de>2023-03-31 15:37:14 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-04-01 15:06:08 +0000
commit8c75d4bd4c42221488b8b231facfe63034d7ad99 (patch)
tree5e7a8aa8e77c4a1d5a0497e186dc0ed8d74928e4 /src/mainboard/google/veyron/reset.c
parent3924e1891d5c1594229fbd00fe0d898f4b449f38 (diff)
soc/amd/stoneyridge: factor out P-state utils to link in all stages
tsc_freq.c gets built into all stages, but the tsc_freq_mhz function it implements calls the get_pstate_0_reg function which was only built into ramstage. Since tsc_freq_mhz was only called in ramstage, commit 2323acab6a7a ("soc/amd/stoneyridge: implement and use get_pstate_0_reg") didn't cause the build to fail, but better factor out the P-state- related utility functions into a separate compilation unit and include it in all stages that also include tsc_freq.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id3a3ee218f495be5e60a888944487704e7e8a1a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/veyron/reset.c')
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