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| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2020-11-30 21:20:13 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-12-04 21:10:19 +0000 |
| commit | ff6a1e5149e0b32ce7141d0354598d81166628f0 (patch) | |
| tree | 1ba9cc7d758bb9265ece3f6e62c373b4016107f9 /src/mainboard/google/veyron/board_info.txt | |
| parent | 99af54e66d1ce2ae8e8d3f4cac91074cbf0aadfa (diff) | |
soc/intel/alderlake: Align chipset.cb with pci_devs.h
Refer pci_devs.h naming to align chipset.cb.
Correct thc0, thc1 and add cnvi_bt.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iac33983dc12ed4e5b9257c50d82adc8e4e728ad6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48153
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/veyron/board_info.txt')
0 files changed, 0 insertions, 0 deletions