diff options
author | Matt DeVillier <matt.devillier@gmail.com> | 2015-12-25 01:15:41 -0600 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-01-21 02:47:29 +0100 |
commit | 89683c0d2676b462be58a09c9a7df55cc1c9b57a (patch) | |
tree | 2b71c55247cca98a3f33acbe8e87f1cff896e6cc /src/mainboard/google/tidus/dsdt.asl | |
parent | 5f4ee47c6c6e9ed0b49f3c39192249a7ab5ceed2 (diff) |
google/tidus: initial upstream migration
Migrate google/tidus (Lenovo ThinkCentre Chromebox) from Chromium
tree to upstream, using google/guado as a baseline.
TEST=built and booted tidus with full functionality
Change-Id: I9d7a976345566bee63226d1a44ba7d5ec137a742
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12801
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/tidus/dsdt.asl')
-rw-r--r-- | src/mainboard/google/tidus/dsdt.asl | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/src/mainboard/google/tidus/dsdt.asl b/src/mainboard/google/tidus/dsdt.asl new file mode 100644 index 0000000000..e0786940c9 --- /dev/null +++ b/src/mainboard/google/tidus/dsdt.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/broadwell/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // CPU + #include <soc/intel/broadwell/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <soc/intel/broadwell/acpi/pch.asl> + } + } + + // Thermal handler + #include "acpi/thermal.asl" + + // Chrome OS specific + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + // Chipset specific sleep states + #include <soc/intel/broadwell/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} |