mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP

These changes are according to spd_binary_optimization_volteer_v0.4 sheet.

Offset     Current value            Updated value       Analysis
1              0x10                    0x11             As per SPD spec rev 1.1
5              0x19                    0x21             16 bits for Row addrs, 10 bits for Column addrs
6              0x95                    0xB5             4 die, 2 ch per pkg, Byte 16 signal matrix
12             0x02                    0x0A             2 ranks per ch, 16 bits device data width
18             0x05                    0x04             4267MHz support
29             0x90                    0xC0             HW specific
30             0x06                    0x68             HW specific
31             0xD0                    0x60             HW specific
32             0x02                    0x04             HW specific
125            0x00                    0xE1             4267MHz support

BUG=b:159319534
TEST=Tested multiple cold boot cycles on TGL-UP3 with QS silicon

Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42524
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions