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author | Matt DeVillier <matt.devillier@gmail.com> | 2020-03-30 02:11:24 -0500 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-31 10:34:42 +0000 |
commit | 61ba3ac92e832259acd831ab6fab2946f57c7035 (patch) | |
tree | b6351d96549e9d6bace8cde0c89dbdbf2e9dd744 /src/mainboard/google/slippy/variants/leon/overridetree.cb | |
parent | 98f609aad4b6d6b6a09efaa011a1f02116935acd (diff) |
mb/google/slippy: Convert variants to use override devicetree
Since the variants' devicetrees are almost identical, convert to
using an overridetree setup for simplicity.
Test: build all slippy variants, compare generated static.c to ensure
resulting generated contents unchanged (although layout will)
Change-Id: If237fad38a1bccfb8e51edfae3ecb75d05ade240
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/slippy/variants/leon/overridetree.cb')
-rw-r--r-- | src/mainboard/google/slippy/variants/leon/overridetree.cb | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/src/mainboard/google/slippy/variants/leon/overridetree.cb b/src/mainboard/google/slippy/variants/leon/overridetree.cb new file mode 100644 index 0000000000..f3b5c4a257 --- /dev/null +++ b/src/mainboard/google/slippy/variants/leon/overridetree.cb @@ -0,0 +1,54 @@ +chip northbridge/intel/haswell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + device domain 0 on + + chip southbridge/intel/lynxpoint + + register "sata_devslp_disable" = "0x1" + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + + device pci 1f.3 on # SMBus + chip drivers/i2c/rtd2132 + # Panel Power Timings (1 ms units) + # Note: the panel Tx timings are very + # different from the LVDS bridge + # Tx timing settings. Below is a mapping + # for RTD2132 -> Panel timings. + # T1 = T2 + # T2 = T8 + T10 + T12 + # T3 = T14 + # T4 = T15 + # T5 = T9 + T11 + T13 + # T6 = T3 + # T7 = T4 + register "t1" = "0x14" + register "t2" = "0xdc" + register "t3" = "0x0e" + register "t4" = "0x02" + register "t5" = "0xdc" + register "t6" = "0x14" + register "t7" = "0x208" + # LVDS Swap settings are normal. + register "lvds_swap" = "0" + # Enable Spread Sprectrum at 0.5% + register "sscg_percent" = "0x05" + device i2c 35 on end # (8bit address: 0x6A) + end # rtd2132 + end # SMBus + end + end +end |