mb/google/skyrim/var/winterhold: update thermal config

Enable STT and set 6 thermal table profiles for Dynamic Thermal Table
Switching Proposal support.

BUG=b:232946420
BRANCH=none
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: Ie0740cb5bb16cd53c2ee6937e32a974346012823
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>

1 files changed, 80 insertions, 16 deletions

diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
index f0c04ab9bb..9d226f106c 100644
--- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
@@ -2,30 +2,21 @@
 
 chip soc/amd/mendocino
 
-	register "system_configuration" = "4"
+	# Set DPTC multi-profile common parameters
 
-	# TODO : Set DPTC confiuration. Table E (SMT)
-	# TODO : Table E as default is only for SMT
-	# TODO : This needs to be cleaned up before b/232946420 can be resolved
-	# TODO : Here is the separate thread number b/258572474 for Table E (SMT)
+	# Refer the spec "FT6 Infrastructure Roadmap"#57316
+	# Set system_configuration to 4 for 15W
+	register "system_configuration" = "4"
 	register "thermctl_limit_degreeC" = "97"
-	register "fast_ppt_limit_mW" = "22000"
-	register "slow_ppt_limit_mW" = "15000"
-	register "slow_ppt_time_constant_s" = "4"
-	register "sustained_power_limit_mW" = "12000"
 
-	# Enable STT support
 	register "stt_control" = "1"
 	register "stt_pcb_sensor_count" = "2"
-	register "stt_min_limit" = "7000"
-	register "stt_m1" = "0x114"
-	register "stt_m2" = "0x371"
-	register "stt_c_apu" = "0xE333"
-	register "stt_alpha_apu" = "0x6666"
-	register "stt_skin_temp_apu" = "0x3000"
+	register "stt_alpha_apu" = "0x199A"
 	register "stt_error_coeff" = "0x21"
 	register "stt_error_rate_coefficient" = "0xCCD"
 
+	# These registers are defined in AMD DevHub document #57316.
+	# Normal
 	register "vrm_current_limit_mA"                  = "28000"
 	register "vrm_maximum_current_limit_mA"          = "50000"
 	register "vrm_soc_current_limit_mA"              = "10000"
@@ -34,6 +25,79 @@ chip soc/amd/mendocino
 	register "vrm_maximum_current_limit_throttle_mA" = "20000"
 	register "vrm_soc_current_limit_throttle_mA"     = "10000"
 
+	# Set Dynamic DPTC thermal profile Table A (Default)
+	register "fast_ppt_limit_mW" = "30000"
+	register "slow_ppt_limit_mW" = "18000"
+	register "slow_ppt_time_constant_s" = "7"
+	register "sustained_power_limit_mW" = "15000"
+
+	register "stt_min_limit" = "7000"
+	register "stt_m1" = "0x148"
+	register "stt_m2" = "0x38F"
+	register "stt_c_apu" = "0xDF9A"
+	register "stt_skin_temp_apu" = "0x3200"
+
+	# Set Dynamic DPTC thermal profile confiuration. Table B
+	register "fast_ppt_limit_mW_B" = "20000"
+	register "slow_ppt_limit_mW_B" = "13000"
+	register "slow_ppt_time_constant_s_B" = "5"
+	register "sustained_power_limit_mW_B" = "10000"
+
+	register "stt_min_limit_B" = "5000"
+	register "stt_m1_B" = "0x11F"
+	register "stt_m2_B" = "0x3AE"
+	register "stt_c_apu_B" = "0xE19A"
+	register "stt_skin_temp_apu_B" = "0x3400"
+
+	# Set Dynamic DPTC thermal profile confiuration. Table C
+	register "fast_ppt_limit_mW_C" = "30000"
+	register "slow_ppt_limit_mW_C" = "22000"
+	register "slow_ppt_time_constant_s_C" = "10"
+	register "sustained_power_limit_mW_C" = "15000"
+
+	register "stt_min_limit_C" = "10000"
+	register "stt_m1_C" = "0x1A4"
+	register "stt_m2_C" = "0x2E1"
+	register "stt_c_apu_C" = "0xDACD"
+	register "stt_skin_temp_apu_C" = "0x3600"
+
+	# Set Dynamic DPTC thermal profile confiuration. Table D
+	register "fast_ppt_limit_mW_D" = "25000"
+	register "slow_ppt_limit_mW_D" = "15000"
+	register "slow_ppt_time_constant_s_D" = "8"
+	register "sustained_power_limit_mW_D" = "10000"
+
+	register "stt_min_limit_D" = "8000"
+	register "stt_m1_D" = "0x1C3"
+	register "stt_m2_D" = "0x2BB"
+	register "stt_c_apu_D" = "0xDE00"
+	register "stt_skin_temp_apu_D" = "0x3800"
+
+	# Set Dynamic DPTC thermal profile confiuration. Table E
+	register "fast_ppt_limit_mW_E" = "22000"
+	register "slow_ppt_limit_mW_E" = "15000"
+	register "slow_ppt_time_constant_s_E" = "4"
+	register "sustained_power_limit_mW_E" = "12000"
+
+	register "stt_min_limit_E" = "7000"
+	register "stt_m1_E" = "0x114"
+	register "stt_m2_E" = "0x371"
+	register "stt_c_apu_E" = "0xE333"
+	register "stt_skin_temp_apu_E" = "0x3000"
+
+
+	# Set Dynamic DPTC thermal profile confiuration. Table F
+	register "fast_ppt_limit_mW_F" = "18000"
+	register "slow_ppt_limit_mW_F" = "12000"
+	register "slow_ppt_time_constant_s_F" = "2"
+	register "sustained_power_limit_mW_F" = "9000"
+
+	register "stt_min_limit_F" = "5000"
+	register "stt_m1_F" = "0x15C"
+	register "stt_m2_F" = "0x33D"
+	register "stt_c_apu_F" = "0xE866"
+	register "stt_skin_temp_apu_F" = "0x3200"
+
 	device domain 0 on
 		device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 			device ref xhci_1 on # XHCI1 controller