diff options
| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2023-02-20 10:27:50 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-04 02:28:45 +0000 |
| commit | 50aa3d99215b558f959fceed891ed04db648739e (patch) | |
| tree | c904632687ea8be392c2ee059789e5561902916f /src/mainboard/google/skyrim/variants/winterhold/overridetree.cb | |
| parent | 12bfe6bc95494f2a993c4222812d8960a66282ba (diff) | |
soc/amd/mendocino: Remove the SPL DPTC parameter
The SPL parameter for DPTC settings is not available for STT-enabled
platforms. It needs to be removed to avoid confusing STT calculations.
BUG=b:265267957
BRANCH=none
TEST=Run the WebGL aquarium with 5000 fish and verify that
there are no power drop peaks.
Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Diffstat (limited to 'src/mainboard/google/skyrim/variants/winterhold/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/skyrim/variants/winterhold/overridetree.cb | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index c9ac6fc0c7..755f96f3b2 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -35,7 +35,6 @@ chip soc/amd/mendocino register "fast_ppt_limit_mW" = "30000" register "slow_ppt_limit_mW" = "25000" register "slow_ppt_time_constant_s" = "5" - register "sustained_power_limit_mW" = "15000" register "stt_min_limit" = "15000" register "stt_m1" = "0x18F" @@ -47,7 +46,6 @@ chip soc/amd/mendocino register "fast_ppt_limit_mW_B" = "15000" register "slow_ppt_limit_mW_B" = "15000" register "slow_ppt_time_constant_s_B" = "5" - register "sustained_power_limit_mW_B" = "10500" register "stt_min_limit_B" = "10500" register "stt_m1_B" = "0x18F" @@ -59,7 +57,6 @@ chip soc/amd/mendocino register "fast_ppt_limit_mW_C" = "30000" register "slow_ppt_limit_mW_C" = "25000" register "slow_ppt_time_constant_s_C" = "5" - register "sustained_power_limit_mW_C" = "15000" register "stt_min_limit_C" = "15000" register "stt_m1_C" = "0x152" @@ -71,7 +68,6 @@ chip soc/amd/mendocino register "fast_ppt_limit_mW_D" = "15000" register "slow_ppt_limit_mW_D" = "15000" register "slow_ppt_time_constant_s_D" = "5" - register "sustained_power_limit_mW_D" = "10500" register "stt_min_limit_D" = "10500" register "stt_m1_D" = "0x152" @@ -83,7 +79,6 @@ chip soc/amd/mendocino register "fast_ppt_limit_mW_E" = "24000" register "slow_ppt_limit_mW_E" = "20000" register "slow_ppt_time_constant_s_E" = "5" - register "sustained_power_limit_mW_E" = "12000" register "stt_min_limit_E" = "12000" register "stt_m1_E" = "0x18F" @@ -96,7 +91,6 @@ chip soc/amd/mendocino register "fast_ppt_limit_mW_F" = "12000" register "slow_ppt_limit_mW_F" = "12000" register "slow_ppt_time_constant_s_F" = "5" - register "sustained_power_limit_mW_F" = "8000" register "stt_min_limit_F" = "8000" register "stt_m1_F" = "0x18F" |