diff options
| author | Krystian Hebel <krystian.hebel@3mdeb.com> | 2018-12-21 18:19:14 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-12-28 22:39:40 +0000 |
| commit | fba03208428fd11acc69e0b3b00bf358cc83f7de (patch) | |
| tree | ade76a3921133b3283f1c4be7c71c0ca3d268788 /src/mainboard/google/sarien | |
| parent | 69b6c56909653f5fd438fbd5d5ffb44d6de7a974 (diff) | |
mb/pcengines/apu2/romstage.c: disable SVI2 wait completion
On some platforms SVI command completion is not reported by
voltage regulator. Because of that CPU got stuck in invalid
P-State, which resulted in lower frequency and inability to
reboot platform without performing cold reset.
Change-Id: I260c997f3a0f4547041785a3b9de78e34d22812a
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/30367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/sarien')
0 files changed, 0 insertions, 0 deletions