diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2019-05-29 23:25:03 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-08-09 01:32:32 +0000 |
| commit | dacd5b9a6ad7d4273af83d356dc869660a04662e (patch) | |
| tree | 7db8e393698e1379dbe5e74f6d2aa264181d656a /src/mainboard/google/sarien | |
| parent | 680027edf6dce0fca22b4e4b9525b1a88cd2ade9 (diff) | |
mb/google/sarien/variants/arcada: Set PCH Thermal Trip point to 77 degree C
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Arcada.
Change-Id: I1915b974b10638b0f6ab97c6fb9b7a58d2cabc59
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/sarien')
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 1799127b6c..ebcf140b4c 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -164,6 +164,9 @@ chip soc/intel/cannonlake register "tcc_offset" = "1" + # PCH Thermal Trip Temperature in deg C + register "common_soc_config.pch_thermal_trip" = "77" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { |