diff options
author | Nico Huber <nico.h@gmx.de> | 2019-10-12 15:16:33 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 15:01:00 +0000 |
commit | 9ea70c02cd0e5e28f38136ebbb6dbad72ad177c7 (patch) | |
tree | 68af4367507ca483522d2013b64c3e2e83511b67 /src/mainboard/google/sarien | |
parent | 95dcf29b2fcc9f7c02812d760ec0be492d5b7580 (diff) |
intel/cannonlake: Implement PCIe RP devicetree update
Some existing devicetrees were manually adapted to anticipate
root-port switching. Now, their PCI-device on/off settings should
just reflect the `PcieRpEnable` state and configuration happens
on the PCI function that was assigned at reset.
Change-Id: I4d76f38c222b74053c6a2f80b492d4660ab4db6d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/sarien')
-rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 6bc3df11af..d1d9b038b2 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -373,10 +373,10 @@ chip soc/intel/cannonlake device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" - end # PCI Express Port 9 - device pci 1d.1 on end # PCI Express Port 10 + end # PCI Express Port 10 device pci 1d.2 on end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on |