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authorFelix Held <felix-coreboot@felixheld.de>2021-12-17 01:50:05 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-12-18 02:06:28 +0000
commit09f7303518c796d7633eb996dfa18ecb26fd6260 (patch)
tree28f8cbfe02ab517ea832dda4b3266ce9c198b564 /src/mainboard/google/sarien
parentf5dfe248ce30ff91a02430b925f3e4bd5dda955a (diff)
soc/amd/common/block/acpimmio/print_reset_status: add missing status bit
Both the Picasso PPR #55570 Rev 3.18 and the Cezanne PPR #56569 Rev 3.03 define bit 9 of the PM_RST_STATUS register as internal Thermal Trip reset status bit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ida8b13fe62b16c18fc9924520b83220e73eca624 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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