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| author | Johnny Lin <johnny_lin@wiwynn.com> | 2020-08-04 18:01:54 +0800 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-07 12:37:04 +0000 |
| commit | 12bee2af237afb6736a91d3f526789efb0542aeb (patch) | |
| tree | cdbb171d08ad8eb95de319498565a6f5800acac0 /src/mainboard/google/sarien/variants | |
| parent | 159d0f0ed7302b214e2e43c5c6041f3d598aab66 (diff) | |
xeon_sp/cpx: Enable HWP Intel Speed Shift
Set HWP base feature, enable EPP, lock thermal interrupt and lock MSR
Tested=On OCP Delta Lake, rdmsr 0x1aa shows 403040
Change-Id: I6d23de4032562095db1aaf96ddfd2b70a4517faa
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44171
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/sarien/variants')
0 files changed, 0 insertions, 0 deletions