diff options
| author | Duncan Laurie <dlaurie@google.com> | 2019-06-13 10:46:54 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-06-13 21:13:58 +0000 |
| commit | de666dc9b86452d5efbda70aa2364877d2fcd449 (patch) | |
| tree | 2362885ae75cb63d83dfb2ad0880ad2bc2d3ad5c /src/mainboard/google/sarien/variants/arcada | |
| parent | 7945f7541717f07c038a0fa4c38130bb1128e2d8 (diff) | |
mb/google/sarien: Disable unused GPIOs
These 4 GPIOs are being disconnected in the next board so use the
board ID to configure these pins as not connected to ensure
they do not cause leakage.
Also remove the ACPI _PTS S5 code that was configuring the GPIOs.
This does mean they will cause small leakage in S5 on existing boards,
but it will not affect the new boards.
BUG=b:132393441
TEST=boot on sarien with fake board ID and ensure that coreboot
configures these pads as expected.
Change-Id: I6ac04b9a635829811a09aeab7cba3bb58cfcff47
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src/mainboard/google/sarien/variants/arcada')
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl index 4b05ba8e90..41121d28fe 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -15,8 +15,6 @@ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 -#define SSD_EN GPP_H13 -#define SSD_RST GPP_H12 /* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -37,13 +35,6 @@ Method (MPTS, 1) /* Clear touch screen pd pin to avoid leakage */ \_SB.PCI0.CTXS (TS_PD) - - /* Clear SSD EN adn RST pin to avoid leakage */ - If (Arg0 == 5) { - \_SB.PCI0.CTXS (SSD_RST) - Sleep(1) - \_SB.PCI0.CTXS (SSD_EN) - } } /* Method called from _WAK prior to wakeup */ |