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authorKrishna Prasad Bhat <krishna.p.bhat.d@intel.com>2019-02-20 15:05:33 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-03-21 16:22:54 +0000
commitcaa85f249d5f8be09ecd7b03e9e87a2fac0190dc (patch)
treeedd5f7473b1ab799fbd47396d4ab7fdd5fd19ce2 /src/mainboard/google/sarien/variants/arcada
parent00bb441ba4f9d427901043db0bb686d389e3adca (diff)
soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports
Assign the FSP UPDs for HPD and DDC of DDI ports. FSP assumes that all DDI ports are enabled and hence configures the HPD and CLK for DDI ports. This patch initializes only the required UPDs to enable display ports. BUG=b:123907904 TEST=DP devices working correctly. Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/sarien/variants/arcada')
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 5e70481bff..6f167c208c 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -41,6 +41,13 @@ chip soc/intel/cannonlake
register "SlowSlewRateForGt" = "0"
register "SlowSlewRateForSa" = "0"
register "SlowSlewRateForFivr" = "0"
+ # Enable eDP device
+ register "DdiPortEdp" = "1"
+ # Enable HPD for DDI ports B/C
+ register "DdiPortBHpd" = "1"
+ register "DdiPortCHpd" = "1"
+ # Enable DDC for DDI port B
+ register "DdiPortBDdc" = "1"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+