diff options
| author | Duncan Laurie <dlaurie@google.com> | 2018-10-31 13:19:21 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-11-02 16:10:07 +0000 |
| commit | 7a70b664c4ba123dfa51a73fca87f67c168bffd3 (patch) | |
| tree | 0947787b273004a67425baab99612f917f2889a2 /src/mainboard/google/sarien/dsdt.asl | |
| parent | 931a579a2e27c1e8f4a752f688e5b02ae57481a8 (diff) | |
mb/google/sarien: Enable Wilco EC
The Sarien mainboard uses the newly added Wilco EC.
- enable CONFIG_EC_GOOGLE_WILCO
- add the device and host command ranges to the devicetree
- have the mainboard SMI handlers call the EC handlers
- add EC and SuperIO devices to the ACPI DSDT
- call the early init hook for serial setup
Change-Id: Idfc4a4af52a613de910ec313d657167918aa2619
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/sarien/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/sarien/dsdt.asl | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 3295078eb9..18fedd5bc9 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <variant/ec.h> + DefinitionBlock( "dsdt.aml", "DSDT", @@ -50,4 +52,15 @@ DefinitionBlock( /* Chipset specific sleep states */ #include <soc/intel/cannonlake/acpi/sleepstates.asl> + +#if IS_ENABLED(CONFIG_EC_GOOGLE_WILCO) + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/wilco/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/wilco/acpi/ec.asl> + } +#endif } |