diff options
author | Duncan Laurie <dlaurie@google.com> | 2018-10-31 10:38:16 -0700 |
---|---|---|
committer | Duncan Laurie <dlaurie@chromium.org> | 2018-11-02 16:07:13 +0000 |
commit | 558602ff4043082f3e0fc91cbf4905302853a94c (patch) | |
tree | b559fe485596ac9b9bc7e75148242bf84988e9ff /src/mainboard/google/sarien/chromeos.fmd | |
parent | db48f7ea48205f69f0c1dd86d71ba0d7fe022d4a (diff) |
mb/google/sarien: Add new mainboard
Sarien is a new board using Intel Whiskey Lake SOC. It also uses
the newly added Wilco EC, enabled in a separate commit.
Sarien is not a true reference board, it is just one variant of
a very similar design. For that reason it is not considered the
baseboard but rather a standalone variant.
Change-Id: I2e38f617694ed2c2ef746ff8083f2bfd58cbc775
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/sarien/chromeos.fmd')
-rw-r--r-- | src/mainboard/google/sarien/chromeos.fmd | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd new file mode 100644 index 0000000000..663176978f --- /dev/null +++ b/src/mainboard/google/sarien/chromeos.fmd @@ -0,0 +1,46 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x1000000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x100000 + SI_GBE@0x101000 0x2000 + SI_ME@0x103000 0xefd000 + } + SI_BIOS@0x1000000 0x1000000 { + RW_SECTION_A@0x0 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x26ffc0 + RW_FWID_A@0x27ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x26ffc0 + RW_FWID_B@0x27ffc0 0x40 + } + RW_MISC@0x500000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 + } + CONSOLE@0x530000 0x20000 + RW_LEGACY(CBFS)@0x550000 0x6b0000 + WP_RO@0xc00000 0x400000 { + RO_VPD@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x3f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x300000 + } + } + } +} |