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authorDuncan Laurie <dlaurie@chromium.org>2014-06-18 14:03:08 +0800
committerMarc Jones <marc.jones@se-eng.com>2015-01-09 07:45:32 +0100
commitc25318938fd9b86969057f3b4e741b949624ec41 (patch)
tree7f0cf74c29f1414ff245dba3b6d3f1092b73345c /src/mainboard/google/samus/spd/hynix_8Gb.spd.hex
parentbb0d5ef97a10bada5310ec7fc4faf53a15e98e71 (diff)
samus: Updates from P2 build
- SPD GPIO table was changed from earlier builds and GPIO67 needs to be swapped with GPIO69 - Hynix 8GB DRAM is actually x16 and needs updated geometry in the SPD - Broadwell LPDDR3 at 1333 is not working in P2, remove the workaround - In order to support both P2A and P2B with one firmware image we need to read the EC board version and use the right SPD GPIO for bit3 - Touchpad I2C address changed to 0x4a/0x26 BUG=chrome-os-partner:29502 BRANCH=None TEST=boot on P2A and P2B boards Original-Change-Id: I4af4161449d904b8dd69c1c4f984b2f41f0dbbbc Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204818 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9cc71b68be556dab154fdf3f86914129e5f7a6dc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic5ca71dbfd9b9d413b86b2ae2786f39fd78ace1d Reviewed-on: http://review.coreboot.org/8135 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/samus/spd/hynix_8Gb.spd.hex')
-rw-r--r--src/mainboard/google/samus/spd/hynix_8Gb.spd.hex8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex b/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex
index 14002c1790..b065b91950 100644
--- a/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex
+++ b/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex
@@ -1,6 +1,6 @@
-# Hynix H9CCNNN8JTMLAR-NTM LPDDR3-S8B 16Gb(x32, 2CS)
-# banks 8, ranks 2, rows 15, columns 10, density 8192 Mb, x32
-92 11 F1 03 05 19 02 0B 03 11 01 08 0A 00 FE 00
+# Hynix H9CCNNNBLTMLAR-NTM LPDDR3
+# banks 8, ranks 2, rows 14, columns 11, density 4096 Mb, x16
+92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00
69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
@@ -8,7 +8,7 @@
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00
-48 39 43 43 4E 4E 4E 38 4A 54 4D 4C 41 52 2D 4E
+48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E
54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00