diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2014-05-22 08:25:36 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-01-04 00:03:54 +0100 |
| commit | 25c6f75bb29fceba7a30d170f2401241fc3428ed (patch) | |
| tree | f05601525d0177b05a915a7243485f4967c28c22 /src/mainboard/google/samus/pei_data.c | |
| parent | fe8b788a12b225ae45ecb26625cfd2588d193ff3 (diff) | |
samus: Update for board revision 1.9
- Update GPIO map
- Update SPD for new memory and 4-bit table decode
- Enable USB3 port 3 and 4 (shared with PCIe port 1)
- Enable PCIe port 3 and disable port 1
- Enable SerialIO ACPI mode for devices
- Disable S0ix for now to prevent use of C10
- Special handling for memory with broadwell CPU
BUG=chrome-os-partner:28234
TEST=Boot on P1.9
Original-Change-Id: If6adcc2ea76f1af7613b715133483d7661e94dd8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201083
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 35835eaed3e098597e46f602fbd646cfbb899355)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Icb03808da6d92705bbc411d155c25de57c4409c6
Reviewed-on: http://review.coreboot.org/8007
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/samus/pei_data.c')
| -rw-r--r-- | src/mainboard/google/samus/pei_data.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/google/samus/pei_data.c b/src/mainboard/google/samus/pei_data.c index c4e9c0bb29..04b86e0d1d 100644 --- a/src/mainboard/google/samus/pei_data.c +++ b/src/mainboard/google/samus/pei_data.c @@ -51,15 +51,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* P1: HOST PORT */ pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1, USB_PORT_BACK_PANEL); - /* P2: EMPTY */ - pei_data_usb2_port(pei_data, 2, 0x0000, 0, USB_OC_PIN_SKIP, - USB_PORT_SKIP); + /* P2: RAIDEN */ + pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); /* P3: SD CARD */ - pei_data_usb2_port(pei_data, 3, 0x0040, 0, USB_OC_PIN_SKIP, + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); - /* P4: EMPTY */ - pei_data_usb2_port(pei_data, 4, 0x0000, 0, USB_OC_PIN_SKIP, - USB_PORT_SKIP); + /* P4: RAIDEN */ + pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); /* P5: WWAN */ pei_data_usb2_port(pei_data, 5, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); @@ -74,8 +74,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) pei_data_usb3_port(pei_data, 0, 1, 0, 0); /* P2: HOST PORT */ pei_data_usb3_port(pei_data, 1, 1, 1, 0); - /* P3: EMPTY */ - pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0); - /* P4: SD CARD */ - pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0); + /* P3: RAIDEN */ + pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); + /* P4: RAIDEN */ + pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); } |