diff options
author | Furquan Shaikh <furquan@google.com> | 2014-08-09 02:04:39 -0700 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-26 00:26:52 +0100 |
commit | d5904c46a091bb58e5ec07287ccb141b319e5ffc (patch) | |
tree | 452d120881888ef154f6b67f129ab1334c15f4dd /src/mainboard/google/rush/romstage.c | |
parent | c41dfb0626eb06616c5d632f7f72c9af29fad331 (diff) |
rush: Convert rush initialization to use funitcfg api
Use funitcfg api for bootblock, romstage as well as ramstage
initialization in rush.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Compiles successfully and boots till last known good point.
Change-Id: I243597de9ec13904a2bb58a04b402f9545424760
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0618ea6828bae3e700b85b79b185aec28568b8ae
Original-Change-Id: I8f5801c1c214f05ef9d2ba976838605da2d8b914
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211766
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8922
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/rush/romstage.c')
-rw-r--r-- | src/mainboard/google/rush/romstage.c | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c index b54058fd38..e82f5ad034 100644 --- a/src/mainboard/google/rush/romstage.c +++ b/src/mainboard/google/rush/romstage.c @@ -23,15 +23,20 @@ #include <soc/clock.h> #include <soc/padconfig.h> #include <soc/nvidia/tegra/i2c.h> - -static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; +#include <soc/funitcfg.h> static const struct pad_config padcfgs[] = { /* SOC_WARM_RESET_L */ PAD_CFG_GPIO_OUT1(GPIO_PI5, PINMUX_PULL_UP), +}; + +static const struct pad_config i2cpad[] = { /* TPM I2C */ PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3), PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3), +}; + +static const struct pad_config spipad[] = { /* EC on SPI1: mosi, miso, clk, cs */ PAD_CFG_SFIO(ULPI_CLK, PINMUX_INPUT_ENABLE, SPI1), PAD_CFG_SFIO(ULPI_DIR, PINMUX_INPUT_ENABLE, SPI1), @@ -39,23 +44,16 @@ static const struct pad_config padcfgs[] = { PAD_CFG_SFIO(ULPI_STP, PINMUX_INPUT_ENABLE, SPI1), }; -static void configure_clocks(void) -{ - /* EC on SPI1 controller. */ - clock_enable_clear_reset(0, CLK_H_SBC1, 0, 0, 0, 0); - clock_configure_source(sbc1, CLK_M, 3000); - - /* TPM on I2C3 controller */ - clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0); - clock_configure_i2c_scl_freq(i2c3, PLLP, 400); -} +static const struct funit_cfg funitcfgs[] = { + FUNIT_CFG(SBC1, CLK_M, 3000, spipad, ARRAY_SIZE(spipad)), + FUNIT_CFG(I2C3, PLLP, 400, i2cpad, ARRAY_SIZE(i2cpad)), +}; void romstage_mainboard_init(void) { - configure_clocks(); - /* Bring up controller interfaces for ramstage loading. */ soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs)); + soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs)); /* TPM I2C bus */ i2c_init(2); |