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authorKun Liu <liukun11@huaqin.corp-partner.google.com>2023-11-30 18:05:03 +0800
committerFelix Held <felix-coreboot@felixheld.de>2023-12-19 13:35:44 +0000
commitf733703a61d291ec300a233bed03c27d53ae6b1f (patch)
tree2bd26e5ea693db8a9b5a0f81eab3a0d783fa94c6 /src/mainboard/google/rex
parentb8fd150da64a54f33971a0a524ec4364eadbce12 (diff)
mb/google/rex/var/screebo: Add delay 1ms after Main 3V3
when S0ix returns S0, PERST needs to delay until Main 3V3 is stable and then pull up BUG=b:313976507 TEST=emerge-rex coreboot,measurement waveform verify pass Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79320 Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/rex')
-rw-r--r--src/mainboard/google/rex/variants/screebo/overridetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb
index f6b32dbdde..86bd74d0b1 100644
--- a/src/mainboard/google/rex/variants/screebo/overridetree.cb
+++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb
@@ -289,6 +289,7 @@ chip soc/intel/meteorlake
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)"
+ register "enable_delay_ms" = "1"
register "srcclk_pin" = "6"
device generic 0 on
probe DB_SD SD_GL9750