mb/google/rex: Optimize FMD usage for rex variants

This patch eliminates the need to maintain separate FMD files for rex
variants and rex variants with ISH. It does this by using the
BOARD_GOOGLE_MODEL_REX_EC_ISH config to differentiate between ME-RW
layout sizes.

TEST=Able to build and boot google/rex and google/rex_ec_ish.

Change-Id: Ibb6ee9aad9fb68198c6c1a1d5978f77d53a2e3ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77895
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 16 insertions, 114 deletions

diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig
index 6af9b699bb..4fd420e58d 100644
--- a/src/mainboard/google/rex/Kconfig
+++ b/src/mainboard/google/rex/Kconfig
@@ -120,8 +120,6 @@ config DEVICETREE
 	default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree.cb"
 
 config FMDFILE
-	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos_ec_ish-debug-fsp.fmd" if CHROMEOS && BOARD_GOOGLE_MODEL_REX_EC_ISH && BUILDING_WITH_DEBUG_FSP
-	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos_ec_ish.fmd" if CHROMEOS && BOARD_GOOGLE_MODEL_REX_EC_ISH
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
 
diff --git a/src/mainboard/google/rex/chromeos-debug-fsp.fmd b/src/mainboard/google/rex/chromeos-debug-fsp.fmd
index c3c13365a9..3fbee83a35 100644
--- a/src/mainboard/google/rex/chromeos-debug-fsp.fmd
+++ b/src/mainboard/google/rex/chromeos-debug-fsp.fmd
@@ -8,7 +8,11 @@ FLASH 32M {
 			VBLOCK_A 8K
 			FW_MAIN_A(CBFS)
 			RW_FWID_A 64
+#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
+			ME_RW_A(CBFS) 4500K
+#else
 			ME_RW_A(CBFS) 4400K
+#endif
 		}
 		# This section starts at the 16M boundary in SPI flash.
 		# MTL does not support a region crossing this boundary,
@@ -18,7 +22,11 @@ FLASH 32M {
 			VBLOCK_B 8K
 			FW_MAIN_B(CBFS)
 			RW_FWID_B 64
+#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
+			ME_RW_B(CBFS) 4500K
+#else
 			ME_RW_B(CBFS) 4400K
+#endif
 		}
 		RW_MISC 1M {
 			UNIFIED_MRC_CACHE(PRESERVE) 128K {
diff --git a/src/mainboard/google/rex/chromeos.fmd b/src/mainboard/google/rex/chromeos.fmd
index b2c0e84b6b..113bc7213e 100644
--- a/src/mainboard/google/rex/chromeos.fmd
+++ b/src/mainboard/google/rex/chromeos.fmd
@@ -8,7 +8,11 @@ FLASH 32M {
 			VBLOCK_A 8K
 			FW_MAIN_A(CBFS)
 			RW_FWID_A 64
+#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
+			ME_RW_A(CBFS) 4500K
+#else
 			ME_RW_A(CBFS) 4400K
+#endif
 		}
 		# This section starts at the 16M boundary in SPI flash.
 		# MTL does not support a region crossing this boundary,
@@ -18,7 +22,11 @@ FLASH 32M {
 			VBLOCK_B 8K
 			FW_MAIN_B(CBFS)
 			RW_FWID_B 64
+#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
+			ME_RW_B(CBFS) 4500K
+#else
 			ME_RW_B(CBFS) 4400K
+#endif
 		}
 		RW_MISC 1M {
 			UNIFIED_MRC_CACHE(PRESERVE) 128K {
diff --git a/src/mainboard/google/rex/chromeos_ec_ish-debug-fsp.fmd b/src/mainboard/google/rex/chromeos_ec_ish-debug-fsp.fmd
deleted file mode 100644
index 22bd1ddff6..0000000000
--- a/src/mainboard/google/rex/chromeos_ec_ish-debug-fsp.fmd
+++ /dev/null
@@ -1,56 +0,0 @@
-FLASH 32M {
-	SI_ALL 9M {
-		SI_DESC 16K
-		SI_ME
-	}
-	SI_BIOS 23M {
-		RW_SECTION_A 7680K {
-			VBLOCK_A 8K
-			FW_MAIN_A(CBFS)
-			RW_FWID_A 64
-			ME_RW_A(CBFS) 4500K
-		}
-		# This section starts at the 16M boundary in SPI flash.
-		# MTL does not support a region crossing this boundary,
-		# because the SPI flash is memory-mapped into two non-
-		# contiguous windows.
-		RW_SECTION_B 7680K {
-			VBLOCK_B 8K
-			FW_MAIN_B(CBFS)
-			RW_FWID_B 64
-			ME_RW_B(CBFS) 4500K
-		}
-		RW_MISC 1M {
-			UNIFIED_MRC_CACHE(PRESERVE) 128K {
-				RECOVERY_MRC_CACHE 64K
-				RW_MRC_CACHE 64K
-			}
-			RW_ELOG(PRESERVE) 16K
-			RW_SHARED 16K {
-				SHARED_DATA 8K
-				VBLOCK_DEV 8K
-			}
-			# The RW_SPD_CACHE region is only used for rex variants that use DDRx memory.
-			# It is placed in the common `chromeos.fmd` file because it is only 4K and there
-			# is free space in the RW_MISC region that cannot be easily reclaimed because
-			# the RW_SECTION_B must start on the 16M boundary.
-			RW_SPD_CACHE(PRESERVE) 4K
-			RW_VPD(PRESERVE) 8K
-			RW_NVRAM(PRESERVE) 24K
-		}
-		RW_LEGACY(CBFS) 1M
-		RW_UNUSED 2M
-		# Make WP_RO region align with SPI vendor
-		# memory protected range specification.
-		WP_RO 4M {
-			RO_VPD(PRESERVE) 16K
-			RO_GSCVD 8K
-			RO_SECTION {
-				FMAP 2K
-				RO_FRID 64
-				GBB@4K 12K
-				COREBOOT(CBFS)
-			}
-		}
-	}
-}
diff --git a/src/mainboard/google/rex/chromeos_ec_ish.fmd b/src/mainboard/google/rex/chromeos_ec_ish.fmd
deleted file mode 100644
index d534fe67f4..0000000000
--- a/src/mainboard/google/rex/chromeos_ec_ish.fmd
+++ /dev/null
@@ -1,56 +0,0 @@
-FLASH 32M {
-	SI_ALL 9M {
-		SI_DESC 16K
-		SI_ME
-	}
-	SI_BIOS 23M {
-		RW_SECTION_A 7M {
-			VBLOCK_A 8K
-			FW_MAIN_A(CBFS)
-			RW_FWID_A 64
-			ME_RW_A(CBFS) 4500K
-		}
-		# This section starts at the 16M boundary in SPI flash.
-		# MTL does not support a region crossing this boundary,
-		# because the SPI flash is memory-mapped into two non-
-		# contiguous windows.
-		RW_SECTION_B 7M {
-			VBLOCK_B 8K
-			FW_MAIN_B(CBFS)
-			RW_FWID_B 64
-			ME_RW_B(CBFS) 4500K
-		}
-		RW_MISC 1M {
-			UNIFIED_MRC_CACHE(PRESERVE) 128K {
-				RECOVERY_MRC_CACHE 64K
-				RW_MRC_CACHE 64K
-			}
-			RW_ELOG(PRESERVE) 16K
-			RW_SHARED 16K {
-				SHARED_DATA 8K
-				VBLOCK_DEV 8K
-			}
-			# The RW_SPD_CACHE region is only used for rex variants that use DDRx memory.
-			# It is placed in the common `chromeos.fmd` file because it is only 4K and there
-			# is free space in the RW_MISC region that cannot be easily reclaimed because
-			# the RW_SECTION_B must start on the 16M boundary.
-			RW_SPD_CACHE(PRESERVE) 4K
-			RW_VPD(PRESERVE) 8K
-			RW_NVRAM(PRESERVE) 24K
-		}
-		RW_LEGACY(CBFS) 1M
-		RW_UNUSED 3M
-		# Make WP_RO region align with SPI vendor
-		# memory protected range specification.
-		WP_RO 4M {
-			RO_VPD(PRESERVE) 16K
-			RO_GSCVD 8K
-			RO_SECTION {
-				FMAP 2K
-				RO_FRID 64
-				GBB@4K 12K
-				COREBOOT(CBFS)
-			}
-		}
-	}
-}