diff options
| author | Kapil Porwal <kapilporwal@google.com> | 2022-08-30 11:54:45 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-08-31 13:56:31 +0000 |
| commit | 4060860942c25872b4e1c8da8e0ab54633ee7f46 (patch) | |
| tree | aa9c4b48fd637c1d2388f78269230cbbeb2f32fb /src/mainboard/google/rex | |
| parent | 5072ed2bb2f104c72e1fe3d1e4b8a5cd06051dad (diff) | |
mb/google/rex: Correct EC-is-trusted logic
Fix EC_IN_RW config for Rex. Dauntless on Rex does not have an EC_IN_RW GPIO pin.
Port of commit 7f339c6050c5 ("mb/google/corsola: Correct EC-is-trusted logic")
BUG=b:243950850
TEST=Built and booted to Google Rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I97e5c752b4f36c9221137903f755837880f6b1c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67208
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Diffstat (limited to 'src/mainboard/google/rex')
| -rw-r--r-- | src/mainboard/google/rex/chromeos.c | 6 | ||||
| -rw-r--r-- | src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h | 2 |
2 files changed, 3 insertions, 5 deletions
diff --git a/src/mainboard/google/rex/chromeos.c b/src/mainboard/google/rex/chromeos.c index 5c99371eb1..217b001a06 100644 --- a/src/mainboard/google/rex/chromeos.c +++ b/src/mainboard/google/rex/chromeos.c @@ -12,7 +12,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } @@ -24,6 +24,6 @@ int get_write_protect_state(void) int get_ec_is_trusted(void) { - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); + /* VB2_CONTEXT_EC_TRUSTED should be set according to the Ti50 boot mode. */ + return 0; } diff --git a/src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h b/src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h index 9da31a69a6..51b9564070 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h +++ b/src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h @@ -9,8 +9,6 @@ /* Fixme: Update proper GPIO number based on schematics */ /* WP signal to PCH */ #define GPIO_PCH_WP GPP_H10 -/* EC in RW or RO */ -#define GPIO_EC_IN_RW 0 /* GPIO IRQ for tight timestamps / wake support */ #define EC_SYNC_IRQ GPP_A17_IRQ /* eSPI virtual wire reporting */ |