diff options
| author | Jamie Ryu <jamie.m.ryu@intel.com> | 2023-10-11 20:16:38 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-10-16 03:42:26 +0000 |
| commit | 15010cd81ff0070e53383769119aab6c66702409 (patch) | |
| tree | 055510025b472fb6070ee4097f52776af0914d1e /src/mainboard/google/rex | |
| parent | 19080a71c85eb8a62d18267f57cc1d01ba7b00dc (diff) | |
mb/google/rex/var/rex: Configure cpu power limits by battery status
When battery level is below critical level or battery is not present,
cpus need to run with a power optimized configuration to avoid platform
instabilities. This will check the current battery status and configure
cpu power limits properly.
BUG=b:296952944
TEST=Build rex0 and check cpu power limits are configured with
a performance efficient configuration and the platform boots to OS if
battery level is above the critical level. And check cpu power limits
are configured with a power optimized configuration and boots to OS
without an issue if battery is not present or battery level is at or
below critical level.
Change-Id: I12fd40abda76c8e7522b06a5aee72665f32ddec8
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78322
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/rex')
| -rw-r--r-- | src/mainboard/google/rex/variants/baseboard/rex/ramstage.c | 33 |
1 files changed, 30 insertions, 3 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c index aee3d888a1..f33db733fa 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c +++ b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c @@ -2,6 +2,7 @@ #include <baseboard/variants.h> #include <device/pci_ids.h> +#include <ec/google/chromeec/ec.h> #include <intelblocks/power_limit.h> /* @@ -9,7 +10,7 @@ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) * Following values are for performance config as per document #640982 */ -const struct cpu_tdp_power_limits limits[] = { +const struct cpu_tdp_power_limits performance_efficient_limits[] = { { .mch_id = PCI_DID_INTEL_MTL_P_ID_2, .cpu_tdp = 15, @@ -21,8 +22,34 @@ const struct cpu_tdp_power_limits limits[] = { }, }; +const struct cpu_tdp_power_limits power_optimized_limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_2, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 57000, + .pl2_max_power = 57000, + .pl4_power = 64000 + }, +}; + void variant_devtree_update(void) { - size_t total_entries = ARRAY_SIZE(limits); - variant_update_cpu_power_limits(limits, total_entries); + const struct cpu_tdp_power_limits *limits = performance_efficient_limits; + size_t limits_size = ARRAY_SIZE(performance_efficient_limits); + + /* + * If battery is not present or battery level is at or below critical threshold + * to boot a platform with the performance efficient configuration, boot with + * the power optimized configuration. + */ + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + if (!google_chromeec_is_battery_present_and_above_critical_threshold()) { + limits = power_optimized_limits; + limits_size = ARRAY_SIZE(power_optimized_limits); + } + } + + variant_update_cpu_power_limits(limits, limits_size); } |