diff options
| author | Eran Mitrani <mitrani@google.com> | 2023-01-10 17:00:11 -0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-08 14:12:25 +0000 |
| commit | 04c3b3234ef758b73bb9a8435347317f26207ed8 (patch) | |
| tree | e6891a8bc443a868ebafc012d3766974baea5744 /src/mainboard/google/rex | |
| parent | e4fc7b0ba6e9b1cdf61278ddd7dfbd17af121b56 (diff) | |
mb/google/rex: Rename touchscreen signals as per latest Rex schematics
Touchscreen signals were renamed for Rex schematics dated 21st Dec'22.
This CL fixes the comments for those signals.
BUG=b:263411413
TEST=None required (changed comments only)
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Ic40ef943d199d9f4a2bec9c0e6d4820224ef6adc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/rex')
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/gpio.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c index 23732f2397..5a854bafc1 100644 --- a/src/mainboard/google/rex/variants/rex0/gpio.c +++ b/src/mainboard/google/rex/variants/rex0/gpio.c @@ -94,9 +94,9 @@ static const struct pad_config gpio_table[] = { /* GPP_B23 : [] ==> WWAN_CONFIG0 */ PAD_CFG_GPI_LOCK(GPP_B23, NONE, LOCK_CONFIG), - /* GPP_C00 : [] ==> EN_PP3300_TCHSCR */ + /* GPP_C00 : [] ==> EN_TCHSCR_PWR */ PAD_CFG_GPO(GPP_C00, 0, DEEP), - /* GPP_C01 : [] ==> USI_RST_L */ + /* GPP_C01 : [] ==> SOC_TCHSCR_RST_L */ PAD_CFG_GPO(GPP_C01, 0, DEEP), /* GPP_C02 : SOC_TCHSCR_SPI_INT_STRAP ==> Component NC */ PAD_NC(GPP_C02, NONE), @@ -257,15 +257,15 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_F12, NONE, DEEP, NF5), /* GPP_F13 : GSPI1_SOC_DI_FPMCU_DO_LS */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF5), - /* GPP_F14 : GSPI_SOC_DO_TCHSCR_DI */ + /* GPP_F14 : GSPI0_SOC_DO_TCHSCR_DI */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8), - /* GPP_F15 : [] ==> GSPI_SOC_DI_TCHSCR_DO */ + /* GPP_F15 : [] ==> GSPI0_SOC_DI_TCHSCR_DO */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8), - /* GPP_F16 : [] ==> GSPI_SOC_TCHSCR_CLK */ + /* GPP_F16 : [] ==> GSPI0_SOC_TCHSCR_CLK */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8), /* GPP_F17 : [] ==> GSPI1_SOC_CS_L */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF5), - /* GPP_F18 : [] ==> GSPI_SOC_TCHSCR_CS_L */ + /* GPP_F18 : [] ==> GSPI0_SOC_TCHSCR_CS_L */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8), /* GPP_F19 : [] ==> GPP_F19_STRAP */ PAD_NC(GPP_F19, NONE), |