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authorEran Mitrani <mitrani@google.com>2022-08-23 14:42:24 -0700
committerSubrata Banik <subratabanik@google.com>2022-11-09 03:36:14 +0000
commitb4d71e1ab2010083f61e218a70abc0ec5803d08b (patch)
treedce20a729e84db50f17d0ae7de53ec2fb9ba7069 /src/mainboard/google/rex/variants/rex0
parent425413c35f443b422feffaee0d1ef8a091998bb6 (diff)
mb/google/rex: Add fingerprint SPI
Add Fingerprint SPI, and power-off FPMCU during romstage. For reference see CL:66915 for a similar change to Brya's power sequence SHA: 2b523ce6316e5c5ec86fe812d739fe48ca81d83d ("Invoke power cycle of FPMCU on startup") TEST=Tested on Rex - setup and logged in using fingerprint Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66992 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/google/rex/variants/rex0')
-rw-r--r--src/mainboard/google/rex/variants/rex0/gpio.c6
-rw-r--r--src/mainboard/google/rex/variants/rex0/overridetree.cb16
2 files changed, 20 insertions, 2 deletions
diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c
index 541402c372..c90c0c11f9 100644
--- a/src/mainboard/google/rex/variants/rex0/gpio.c
+++ b/src/mainboard/google/rex/variants/rex0/gpio.c
@@ -432,8 +432,12 @@ static const struct pad_config default_early_gpio_table[] = {
};
static const struct pad_config romstage_gpio_table_id0[] = {
- /* A20 : [] ==> SSD_PERST_L */
+ /* GPP_B11 : [] ==> EN_FP_PWR */
+ PAD_CFG_GPO(GPP_B11, 0, DEEP),
+ /* A20 : [] ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_A20, 0, DEEP),
+ /* GPP_C23 : [] ==> FP_RST_ODL */
+ PAD_CFG_GPO(GPP_C23, 0, DEEP),
/* GPP_E07 : [] ==> WWAN_FCPO_L */
PAD_CFG_GPO(GPP_E07, 1, DEEP),
};
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index 00cbe8c5b8..a7f5a95c32 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -471,7 +471,21 @@ chip soc/intel/meteorlake
device generic 0 on end
end
end #PCIE6 WWAN card
- device ref gspi1 on end
+ device ref gspi1 on
+ chip drivers/spi/acpi
+ register "name" = ""CRFP""
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "uid" = "1"
+ register "compat_string" = ""google,cros-ec-spi""
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E10_IRQ)"
+ register "wake" = "GPE0_DW1_10"
+ register "has_power_resource" = "1"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C23)"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
+ register "enable_delay_ms" = "3"
+ device spi 0 on end
+ end # FPMCU
+ end
device ref soc_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]