diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-06-27 09:21:37 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-06-28 16:46:17 +0000 |
| commit | dc69b15ed7e7fb89e52d9abec104c54e26bd1456 (patch) | |
| tree | fa4dd308bc8a43ff30603be23318608f70a3a97e /src/mainboard/google/rex/variants/baseboard | |
| parent | 854de98d648f5b9526bd3fef5cee3b507eb65839 (diff) | |
mb/google/rex: Avoid boot hang due to missing SOC/IOE SRAM device
The SOC/IOE SRAM device is used to store crash logs. Previously, the
crashlog enablement was hardcoded in the baseboard.common module.
This commit moves the crashlog enablement logic to the baseboard
module, so that it can be enabled or disabled based on the specific
baseboard.
Additionally, the SOC/IOE SRAM is now enabled by default in the
baseboard devicetree.cb file. This prevents the system from hanging
if the SOC/IOE SRAM device is not present.
BUG=b:262501347
TEST=Able to build and boot google/screebo with this patch.
w/o this patch:
[ERROR] SOC SRAM device not found!
[ERROR] IOE SRAM base not valid
Change-Id: I02d581e5b62cfa114a3761a9704ad9f24dead8aa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/mainboard/google/rex/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 7acc0ae047..76b9dcd82a 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -73,6 +73,7 @@ chip soc/intel/meteorlake device domain 0 on device ref igpu on end device ref dtt on end + device ref ioe_shared_sram on end device ref xhci on end device ref pmc_shared_sram on end device ref heci1 on end |