mb/google/rex: Create ovis variant

BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a ; Make sure
GOOGLE_OVIS built successfully

Change-Id: I5c8f290cfdcb4d47c0e5e9d72c1e34073b957681
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75385
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 256 insertions, 0 deletions

diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/Makefile.inc b/src/mainboard/google/rex/variants/baseboard/ovis/Makefile.inc
new file mode 100644
index 0000000000..fd45b948ff
--- /dev/null
+++ b/src/mainboard/google/rex/variants/baseboard/ovis/Makefile.inc
@@ -0,0 +1 @@
+romstage-y += memory.c
diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
new file mode 100644
index 0000000000..9a71e959c3
--- /dev/null
+++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
@@ -0,0 +1,69 @@
+chip soc/intel/meteorlake
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_E"
+	register "pmc_gpe0_dw2" = "GPP_F"
+
+	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
+	# EC memory map range is 0x900-0x9ff
+	register "gen3_dec" = "0x00fc0901"
+
+	register "usb2_ports[0]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 0
+	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 1
+	register "usb2_ports[2]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 2
+	register "usb2_ports[3]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 3
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 4
+	register "usb2_ports[5]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 5
+	register "usb2_ports[6]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 6
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 7
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 8
+	register "usb2_ports[9]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 9
+
+	register "usb3_ports[0]" = "USB3_PORT_EMPTY"	# Disable USB3.0 Port 0
+	register "usb3_ports[1]" = "USB3_PORT_EMPTY"	# Disable USB3.0 Port 1
+
+	register "tcss_ports[0]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 0
+	register "tcss_ports[1]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 1
+	register "tcss_ports[2]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 2
+	register "tcss_ports[3]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 3
+
+	# S0ix enable
+	register "s0ix_enable" = "1"
+
+	# DPTF enable
+	register "dptf_enable" = "1"
+
+	# Enable CNVi BT
+	register "cnvi_bt_core" = "true"
+
+	# Set on-board graphics as primary display
+	register "skip_ext_gfx_scan" = "1"
+
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
+
+	device domain 0 on
+		device ref igpu on end
+		device ref dtt on end
+		device ref xhci on end
+		device ref shared_sram on end
+		device ref heci1 on end
+		device ref uart0 on end
+		device ref soc_espi on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/ec.h b/src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/ec.h
new file mode 100644
index 0000000000..a0f47d9360
--- /dev/null
+++ b/src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/ec.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <baseboard/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_NONE)
+/* EC can wake from S5 with power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+/*
+ * EC can wake from S3/S0ix with:
+ * 1. AC Connect/Disconnect
+ * 2. Power button
+ * 3. Key press
+ * 4. Mode change
+ */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
+	(MAINBOARD_EC_S3_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)         |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+/*
+ * ACPI related definitions for ASL code.
+ */
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+/* Enable MKBP for buttons and switches */
+#define EC_ENABLE_MKBP_DEVICE
+#define EC_ENABLE_WAKE_PIN      GPE_EC_WAKE
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+#define SIO_EC_MEMMAP_ENABLE     /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE       /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K       /* Enable PS/2 Keyboard */
+
+#define EC_ENABLE_SYNC_IRQ      /* Enable tight timestamp / wake support */
+
+#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/gpio.h b/src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/gpio.h
new file mode 100644
index 0000000000..35e055b7ed
--- /dev/null
+++ b/src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/gpio.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* WP signal to PCH */
+#define GPIO_PCH_WP	GPP_H10
+/* GPIO IRQ for tight timestamps / wake support */
+#define EC_SYNC_IRQ	GPP_A17_IRQ
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI	GPE0_ESPI
+/* Used to gate SoC's SLP_S0# signal */
+#define GPIO_SLP_S0_GATE	GPP_H14
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE	GPE0_LAN_WAK
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0	GPP_E11
+#define GPIO_MEM_CONFIG_1	GPP_E02
+#define GPIO_MEM_CONFIG_2	GPP_E01
+#define GPIO_MEM_CONFIG_3	GPP_E12
+#define GPIO_MEM_CH_SEL		GPP_E13
+
+#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/memory.c b/src/mainboard/google/rex/variants/baseboard/ovis/memory.c
new file mode 100644
index 0000000000..1541cec950
--- /dev/null
+++ b/src/mainboard/google/rex/variants/baseboard/ovis/memory.c
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-3.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+
+static const struct mb_cfg baseboard_memcfg = {
+	.type = MEM_TYPE_LP5X,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+	},
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  7,  1,  2,  0,  3,  6,  5,  4 },
+			.dq1 = { 13, 12, 14, 15,  8,  9, 10, 11 },
+		},
+		.ddr1 = {
+			.dq0 = { 10,  9, 11,  8, 15, 13, 14, 12 },
+			.dq1 = {  6,  0,  7,  4,  3,  1,  2,  5 },
+		},
+		.ddr2 = {
+			.dq0 = { 11, 10,  8,  9, 12, 15, 14, 13 },
+			.dq1 = {  7,  0,  6,  5,  3,  2,  1,  4 },
+		},
+		.ddr3 = {
+			.dq0 = { 13, 10,  8,  9, 14, 11, 15, 12 },
+			.dq1 = {  1,  6,  4,  7,  0,  5,  2,  3 },
+		},
+		.ddr4 = {
+			.dq0 = { 10, 11,  9, 12, 13, 14, 15,  8 },
+			.dq1 = {  6,  7,  4,  5,  1,  0,  3,  2 },
+		},
+		.ddr5 = {
+			.dq0 = {  0,  5,  3,  6,  1,  4,  2,  7 },
+			.dq1 = {  8, 11, 10,  9, 15, 14, 13, 12 },
+		},
+		.ddr6 = {
+			.dq0 = {  1,  3,  0,  2,  6,  5,  7,  4 },
+			.dq1 = { 13, 15, 14, 12, 11, 10,  8,  9 },
+		},
+		.ddr7 = {
+			.dq0 = { 10,  9, 11,  8, 12, 15, 14, 13 },
+			.dq1 = {  6,  4,  7,  5,  2,  1,  0,  3 },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr2 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr7 = { .dqs0 = 1, .dqs1 = 0 },
+	},
+
+	.lp5x_config = {
+		.ccc_config = 0x66,
+	},
+
+	.ect = 1, /* Early Command Training */
+};
+
+const struct mb_cfg *__weak variant_memory_params(void)
+{
+	return &baseboard_memcfg;
+}
+
+int __weak variant_memory_sku(void)
+{
+	gpio_t spd_gpios[] = {
+		GPIO_MEM_CONFIG_0,
+		GPIO_MEM_CONFIG_1,
+		GPIO_MEM_CONFIG_2,
+		GPIO_MEM_CONFIG_3,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+bool __weak variant_is_half_populated(void)
+{
+	return gpio_get(GPIO_MEM_CH_SEL);
+}
+
+void __weak variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+}