mb/google/{rex, ovis}: Introduce devicetree.cb for pre-prod SoC

This patch introduces a dedicated devicetree.cb file for platforms
built with pre-production SoC. This will help to keep the SoC
configuration separate for platforms with ESx and QSx silicons.

For example, the SaGv WP configuration is different between
pre-production (aka ESx) and production (aka QSx) silicon.

BUG=b:306267652
TEST=Able to build and boot google/rex4es.

Change-Id: I01b0abeeb25ce5a83882c56b30929228fcc6c95c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com>

2 files changed, 106 insertions, 12 deletions

diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
index 7d39ece8c0..3f75b709da 100644
--- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
@@ -53,19 +53,17 @@ chip soc/intel/meteorlake
 
 	register "sagv" = "SAGV_ENABLED"
 
-	register "sagv_freq_mhz" = "{
-		[0] = 3200,
-		[1] = 6000,
-		[2] = 6400,
-		[3] = 5600,
-	}"
+	register "sagv_freq_mhz[0]" = "2133"
+	register "sagv_gear[0]" = "4"
 
-	register "sagv_gear" = "{
-		[0] = 4,
-		[1] = 4,
-		[2] = 4,
-		[3] = 2,
-	}"
+	register "sagv_freq_mhz[1]" = "4267"
+	register "sagv_gear[1]" = "4"
+
+	register "sagv_freq_mhz[2]" = "6000"
+	register "sagv_gear[2]" = "4"
+
+	register "sagv_freq_mhz[3]" = "6400"
+	register "sagv_gear[3]" = "4"
 
 	# Set on-board graphics as primary display
 	register "skip_ext_gfx_scan" = "1"
diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb
new file mode 100644
index 0000000000..0835ded2f2
--- /dev/null
+++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb
@@ -0,0 +1,96 @@
+chip soc/intel/meteorlake
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "GPP_D"
+	register "pmc_gpe0_dw1" = "GPP_E"
+	register "pmc_gpe0_dw2" = "GPP_F"
+
+	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
+	# EC memory map range is 0x900-0x9ff
+	register "gen3_dec" = "0x00fc0901"
+
+	register "usb2_ports[0]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 0
+	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 1
+	register "usb2_ports[2]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 2
+	register "usb2_ports[3]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 3
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 4
+	register "usb2_ports[5]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 5
+	register "usb2_ports[6]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 6
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 7
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 8
+	register "usb2_ports[9]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 9
+
+	register "usb3_ports[0]" = "USB3_PORT_EMPTY"	# Disable USB3.0 Port 0
+	register "usb3_ports[1]" = "USB3_PORT_EMPTY"	# Disable USB3.0 Port 1
+
+	register "tcss_ports[0]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 0
+	register "tcss_ports[1]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 1
+	register "tcss_ports[2]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 2
+	register "tcss_ports[3]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 3
+
+	# S0ix enable
+	register "s0ix_enable" = "1"
+
+	# Disable C1 C-state auto-demotion
+	register "disable_c1_state_auto_demotion" = "1"
+
+	# Disable PKGC-state demotion
+	register "disable_package_c_state_demotion" = "1"
+
+	# Enable Energy Reporting
+	register "pch_pm_energy_report_enable" = "1"
+
+	# DPTF enable
+	register "dptf_enable" = "1"
+
+	# Temporary setting TCC of 100C = Tj max (110) - TCC_Offset (10)
+	register "tcc_offset" = "10"
+
+	# Enable CNVi BT
+	register "cnvi_bt_core" = "true"
+
+	register "sagv" = "SAGV_ENABLED"
+
+	register "sagv_freq_mhz[0]" = "3200"
+	register "sagv_gear[0]" = "4"
+
+	register "sagv_freq_mhz[1]" = "6000"
+	register "sagv_gear[1]" = "4"
+
+	register "sagv_freq_mhz[2]" = "6400"
+	register "sagv_gear[2]" = "4"
+
+	register "sagv_freq_mhz[3]" = "5600"
+	register "sagv_gear[3]" = "2"
+
+	# Set on-board graphics as primary display
+	register "skip_ext_gfx_scan" = "1"
+
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
+
+	device domain 0 on
+		device ref igpu on end
+		device ref dtt on end
+		device ref ioe_shared_sram on end
+		device ref xhci on end
+		device ref pmc_shared_sram on end
+		device ref heci1 on end
+		device ref uart0 on end
+		device ref soc_espi on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end
+	end
+end