diff options
| author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2016-11-09 14:07:30 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-10 16:52:16 +0100 |
| commit | c4943d86b07f1e09cd1033ead3d4e1f4ea498c57 (patch) | |
| tree | b45a18df9218919959d4986ff76464b3814d37c3 /src/mainboard/google/reef | |
| parent | 961d6d45a6c5520c7a379c4d9b3002d1e8320e3e (diff) | |
mainboard/google/pyro: Set PL1 override to 12000mW
Pyro is using APL SoC SKU's with 6W TDP max. As Reef,
the energy calculation is wrong with the current VR solution.
Experiments show that SoC TDP max (6W) can be reached
when RAPL PL1 is set to 12W.
Therefore, we've inserted 12W override after reading the fused value (6W)
so that the system can reach the right performance level.
BUG=chrome-os-partner:58112
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: I6de22d7b2d107f3d26ecfadd4e0904e68318e656
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17335
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/google/reef')
| -rw-r--r-- | src/mainboard/google/reef/variants/pyro/devicetree.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 7405b37edc..da893b1d36 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -49,6 +49,11 @@ chip soc/intel/apollolake # Enable DPTF register "dptf_enable" = "1" + # PL1 override 12000 mW: the energy calculation is wrong with the + # current VR solution. Experiments show that SoC TDP max (6W) can + # be reached when RAPL PL1 is set to 12W. + register "tdp_pl1_override_mw" = "12000" + # Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" register "hdaudio_pwr_gate_enable" = "1" |