From c4943d86b07f1e09cd1033ead3d4e1f4ea498c57 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Wed, 9 Nov 2016 14:07:30 +0800 Subject: mainboard/google/pyro: Set PL1 override to 12000mW Pyro is using APL SoC SKU's with 6W TDP max. As Reef, the energy calculation is wrong with the current VR solution. Experiments show that SoC TDP max (6W) can be reached when RAPL PL1 is set to 12W. Therefore, we've inserted 12W override after reading the fused value (6W) so that the system can reach the right performance level. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot chromeos-bootimage Change-Id: I6de22d7b2d107f3d26ecfadd4e0904e68318e656 Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/17335 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mainboard/google/reef') diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 7405b37edc..da893b1d36 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -49,6 +49,11 @@ chip soc/intel/apollolake # Enable DPTF register "dptf_enable" = "1" + # PL1 override 12000 mW: the energy calculation is wrong with the + # current VR solution. Experiments show that SoC TDP max (6W) can + # be reached when RAPL PL1 is set to 12W. + register "tdp_pl1_override_mw" = "12000" + # Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" register "hdaudio_pwr_gate_enable" = "1" -- cgit v1.2.3