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authorVaibhav Shankar <vaibhav.shankar@intel.com>2016-09-15 14:02:54 -0700
committerMartin Roth <martinroth@google.com>2016-09-19 19:33:31 +0200
commit767009aeab7986faa2a86b7c33fdc2a303583139 (patch)
tree08724691bb22171334f05f89a969d2e8cab7e52c /src/mainboard/google/reef/variants
parentec9168f52b734bb6ea116cdd28407dbabc784f5d (diff)
mainboard/google/reef: Configure WLAN as wake source
This implements PRW method for WLAN and configures PCIe wake pin to generate SCI. BUG=chrome-os-partner:56483 TEST=Suspend the system into S3 or S0ix. System should resume through wake event from wifi. Change-Id: I9bd078c2de19ebcc652b5d981997d2a5b5f0b1b7 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16611 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/google/reef/variants')
-rw-r--r--src/mainboard/google/reef/variants/baseboard/devicetree.cb7
-rw-r--r--src/mainboard/google/reef/variants/baseboard/gpio.c2
2 files changed, 7 insertions, 2 deletions
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index c83df61f59..f1ce8c58e0 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -94,7 +94,12 @@ chip soc/intel/apollolake
device pci 13.1 off end # - Root Port 3 - PCIe-A 1
device pci 13.2 off end # - Root Port 4 - PCIe-A 2
device pci 13.3 off end # - Root Port 5 - PCIe-A 3
- device pci 14.0 on end # - Root Port 0 - PCIe-B 0 - Wifi
+ device pci 14.0 on
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_DW3_00"
+ device pci 00.0 on end
+ end
+ end # - Root Port 0 - PCIe-B 0 - Wifi
device pci 14.1 off end # - Root Port 1 - PCIe-B 1
device pci 15.0 on end # - XHCI
device pci 15.1 off end # - XDCI
diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c
index eb1b2ebc74..7d74140c78 100644
--- a/src/mainboard/google/reef/variants/baseboard/gpio.c
+++ b/src/mainboard/google/reef/variants/baseboard/gpio.c
@@ -24,7 +24,7 @@
*/
static const struct pad_config gpio_table[] = {
/* PCIE_WAKE[0:3]_N */
- PAD_CFG_NF(GPIO_205, UP_20K, DEEP, NF1), /* WLAN */
+ PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE), /* WLAN */
PAD_CFG_GPI(GPIO_206, UP_20K, DEEP), /* Unused */
PAD_CFG_GPI(GPIO_207, UP_20K, DEEP), /* Unused */
PAD_CFG_GPI(GPIO_208, UP_20K, DEEP), /* Unused */