soc/intel/common/block: Add common chip config block

Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.

For now, adding i2c, gspi and lockdown configuration which will be used
by common code.

BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.

Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 37 insertions, 34 deletions

diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index 9719368080..aaf61de6ae 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -76,40 +76,43 @@ chip soc/intel/apollolake
 	register "gpe0_dw2" = "PMC_GPE_N_63_32"
 	register "gpe0_dw3" = "PMC_GPE_SW_31_0"
 
-	# Enable I2C0 for audio codec at 400kHz
-	register "i2c[0]" = "{
-		.speed = I2C_SPEED_FAST,
-		.rise_time_ns = 44,
-		.fall_time_ns = 22,
-	}"
-
-	# Enable I2C2 bus early for TPM at 400kHz
-	register "i2c[2]" = "{
-		.early_init = 1,
-		.speed = I2C_SPEED_FAST,
-		.rise_time_ns = 40,
-		.fall_time_ns = 20,
-	}"
-
-	# touchscreen at 400kHz
-	register "i2c[3]" = "{
-		.speed = I2C_SPEED_FAST,
-		.rise_time_ns = 70,
-		.fall_time_ns = 164,
-	}"
-
-	# trackpad at 400kHz
-	register "i2c[4]" = "{
-		.speed = I2C_SPEED_FAST,
-		.rise_time_ns = 20,
-		.fall_time_ns = 164,
-	}"
-
-	# digitizer at 400kHz
-	register "i2c[5]" = "{
-		.speed = I2C_SPEED_FAST,
-		.rise_time_ns = 152,
-		.fall_time_ns = 30,
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | Audio                     |
+	#| I2C2              | TPM                       |
+	#| I2C3              | Touchscreen               |
+	#| I2C4              | Trackpad                  |
+	#| I2C5              | Digitizer                 |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 44,
+			.fall_time_ns = 22,
+		},
+		.i2c[2] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 40,
+			.fall_time_ns = 20,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 70,
+			.fall_time_ns = 164,
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 20,
+			.fall_time_ns = 164,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 152,
+			.fall_time_ns = 30,
+		},
 	}"
 
 	# Minimum SLP S3 assertion width 28ms.