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| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-02-01 08:02:23 +0100 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-02-03 19:55:53 +0000 |
| commit | 64e2ecb36fd1d7b289cd9671dcfae2e335528d81 (patch) | |
| tree | a48c10aa42b234c85e8afaf28d0f11231e275e28 /src/mainboard/google/reef/variants/baseboard/devicetree.cb | |
| parent | a10a86d2bc8d3daf9394ccb0c7e0479ad1eec6e5 (diff) | |
soc/intel/apl: Move cpu cluster to chipset.cb
Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Diffstat (limited to 'src/mainboard/google/reef/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/reef/variants/baseboard/devicetree.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 2199ac0912..d24e67be51 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" |