diff options
| author | Yidi Lin <yidilin@chromium.org> | 2024-04-15 10:23:23 +0800 |
|---|---|---|
| committer | Yu-Ping Wu <yupingso@google.com> | 2024-11-13 02:48:03 +0000 |
| commit | a7ed63cbc8e2f2f9bd874a35653e8da213ad6151 (patch) | |
| tree | f91592b29924780011f770e35fde12ab7554048c /src/mainboard/google/rauru/bootblock.c | |
| parent | 613c5f9ff23c497ec9d98893ef93676962cb3213 (diff) | |
mb/google/rauru: Configure TPM
1. Add Google Ti50 TPM support
2. Configure I2C speed to I2C_SPEED_FAST_PLUS
3. Pass GPIO_GSC_AP_INT_ODL to the payload
4. Configure IRQ type to IRQ_TYPE_EDGE_RISING for now
BUG=b:317009620
TEST=build pass, boot ok and there is no CR50 TPM timeout log
Pass log:
[INFO ] Probing TPM I2C: done! DID_VID 0x504a6666
[DEBUG] GSC TPM 2.0 (i2c 1:0x50 id 0x504a)
Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84932
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Diffstat (limited to 'src/mainboard/google/rauru/bootblock.c')
| -rw-r--r-- | src/mainboard/google/rauru/bootblock.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/rauru/bootblock.c b/src/mainboard/google/rauru/bootblock.c index bbebf5228c..6e0a4eea16 100644 --- a/src/mainboard/google/rauru/bootblock.c +++ b/src/mainboard/google/rauru/bootblock.c @@ -2,6 +2,8 @@ #include <bootblock_common.h> #include <gpio.h> +#include <soc/gpio.h> +#include <soc/i2c.h> #include <soc/pcie.h> #include <soc/spi.h> @@ -17,8 +19,10 @@ void bootblock_mainboard_init(void) if (CONFIG(PCI)) mtk_pcie_pre_init(); + mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST_PLUS); mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); mtk_snfc_init(); usb3_hub_reset(); setup_chromeos_gpios(); + gpio_eint_configure(GPIO_GSC_AP_INT_ODL, IRQ_TYPE_EDGE_RISING); } |