Combine Baytrail ChromeOS devices using variant scheme

Combine existing boards google/enguarde and google/ninja using
their common reference board google/rambi as a baseboard.

Variants contain board specific data:
 - DPTF ACPI components
 - I2C ACPI devices
 - RAM config / SPD data
 - devicetree config
 - GPIOs
 - board-specific HW components (e.g., LAN)

Additionally, some minor cleanup/changes were made:
 - remove unused ACPI trackpad/touchscreen devices
 - correct I2C addresses in SMBIOS entries
 - clean up comment formatting
 - remove ACPI device for unused light sensor
 - switch I2C ACPI devices from edge to level triggered interrupts,
   for better compatibility/functionality (and to be consistent
   with other recently-upstreamed ChromeOS devices)

The existing enguarde and ninja boards are removed.

Variant setup modeled after google/auron

Change-Id: Iae7855af9a224fd4cb948b854494e39b545ad449
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18129
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

4 files changed, 120 insertions, 0 deletions

diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000000..7ab3356350
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/dptf.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	80
+#define DPTF_CPU_CRITICAL	105
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	48
+#define DPTF_TSR0_CRITICAL	80
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	60
+#define DPTF_TSR1_CRITICAL	80
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	55
+#define DPTF_TSR2_CRITICAL	80
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 },	/* 0.128A */
+})
diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/mainboard.asl
diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h b/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h
new file mode 100644
index 0000000000..ec8bcd6f89
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/rambi/irqroute.h>
+
+#ifndef __ACPI__
+void lan_init(void);
+#endif
+
+/* defines for programming the MAC address */
+#define NINJA_NIC_VENDOR_ID			0x10EC
+#define NINJA_NIC_DEVICE_ID			0x8168
+
+/* 0x00: White LINK LED and Amber ACTIVE LED */
+#define NINJA_NIC_LED_MODE			0x00
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO             ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+
+/* Disable PS2 keyboard */
+#undef SIO_EC_ENABLE_PS2K
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h b/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h
new file mode 100644
index 0000000000..8d2113c063
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_H
+#define VARIANT_H
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+ * 0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz
+ * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b110 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+ * 0b111 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+ */
+
+static const uint32_t dual_channel_config =
+	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+
+#endif