Combine Baytrail ChromeOS devices using variant scheme

Combine existing boards google/enguarde and google/ninja using
their common reference board google/rambi as a baseboard.

Variants contain board specific data:
 - DPTF ACPI components
 - I2C ACPI devices
 - RAM config / SPD data
 - devicetree config
 - GPIOs
 - board-specific HW components (e.g., LAN)

Additionally, some minor cleanup/changes were made:
 - remove unused ACPI trackpad/touchscreen devices
 - correct I2C addresses in SMBIOS entries
 - clean up comment formatting
 - remove ACPI device for unused light sensor
 - switch I2C ACPI devices from edge to level triggered interrupts,
   for better compatibility/functionality (and to be consistent
   with other recently-upstreamed ChromeOS devices)

The existing enguarde and ninja boards are removed.

Variant setup modeled after google/auron

Change-Id: Iae7855af9a224fd4cb948b854494e39b545ad449
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18129
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

7 files changed, 512 insertions, 0 deletions

diff --git a/src/mainboard/google/rambi/variants/enguarde/Makefile.inc b/src/mainboard/google/rambi/variants/enguarde/Makefile.inc
new file mode 100644
index 0000000000..5e0042acd4
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/enguarde/Makefile.inc
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+# 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+# 0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz
+# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+# 0b101 - 2GiB total - 2 x 1GiB Samsung K4B2G1646Q-BYK0 1600MHz
+# 0b110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+# 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125
+SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA
+SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125
+SPD_SOURCES += samsung_1GiB_dimm_K4B2G1646Q-BYK0
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/rambi/variants/enguarde/devicetree.cb b/src/mainboard/google/rambi/variants/enguarde/devicetree.cb
new file mode 100644
index 0000000000..f3792fe70a
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/enguarde/devicetree.cb
@@ -0,0 +1,101 @@
+chip soc/intel/baytrail
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x1"
+	register "sata_ahci" = "0x1"
+	register "ide_legacy_combined" = "0x0"
+
+	# Route USB ports to XHCI
+	register "usb_route_to_xhci" = "1"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	# TODO: These values are from Baytrail and need tuned for Enguarde board
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# SD Card controller
+	register "sdcard_cap_low" = "0x036864b2"
+	register "sdcard_cap_high" = "0x0"
+
+	# Enable devices in ACPI mode
+	register "lpe_acpi_mode" = "1"
+	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	# Enable PIPEA as DP_C
+	register "gpu_pipea_port_select" = "2"		# DP_C
+	register "gpu_pipea_power_cycle_delay" = "6"	# 600ms
+	register "gpu_pipea_power_on_delay" = "5000"	# 500ms
+	register "gpu_pipea_light_on_delay" = "70"	# 7ms
+	register "gpu_pipea_power_off_delay" = "500"	# 50ms
+	register "gpu_pipea_light_off_delay" = "2000"	# 200ms
+
+	# VR PS2 control
+	register "vnn_ps2_enable" = "1"
+	register "vcc_ps2_enable" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 11.0 off end # SDIO
+		device pci 12.0 on  end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 on  end # LPE
+		device pci 17.0 on  end # MMC
+		device pci 18.0 on  end # SIO_DMA1
+		device pci 18.1 on  end # I2C1
+		device pci 18.2 on  end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 on  end # I2C5
+		device pci 18.6 off  end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 on  end # HDA
+		device pci 1c.0 on  end # PCIE_PORT1
+		device pci 1c.1 on  end # PCIE_PORT2
+		device pci 1c.2 off end # PCIE_PORT3
+		device pci 1c.3 off end # PCIE_PORT4
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 on  end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end # SMBus
+	end
+end
diff --git a/src/mainboard/google/rambi/variants/enguarde/gpio.c b/src/mainboard/google/rambi/variants/enguarde/gpio.c
new file mode 100644
index 0000000000..2802aa6495
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/enguarde/gpio.c
@@ -0,0 +1,230 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include <mainboard/google/rambi/irqroute.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,	/* S0_NC00 - INT_HDMI_HPD - INT */
+	GPIO_FUNC2,	/* S0_NC01 - HDMI_DDCDATA_SW */
+	GPIO_FUNC2,	/* S0_NC02 - HDMI_DDCCLK_SW */
+	GPIO_NC,	/* S0_NC03 - NC */
+	GPIO_NC,	/* S0_NC04 - NC */
+	GPIO_NC,	/* S0_NC05 - NC */
+	GPIO_FUNC2,	/* S0_NC06 - EDP_HPD_L */
+	GPIO_INPUT,	/* S0_NC07 - DDI1_DDCDATA - STRAP */
+	GPIO_NC,	/* S0_NC08 - NC */
+	GPIO_OUT_HIGH,	/* S0_NC09 - SOC_DISP_ON_C */
+	GPIO_FUNC2,	/* S0_NC10 - SOC_EDP_BLON_C */
+	GPIO_FUNC2,	/* S0_NC11 - SOC_DPST_PWM_C */
+	GPIO_NC,	/* S0_NC12 - NC */
+	GPIO_INPUT,	/* S0_NC13 - GPIO_NC13 - STRAP */
+	GPIO_NC,	/* S0_NC14 - NC */
+	GPIO_DEFAULT,	/* S0_NC15 - XDP_GPIO_S0_NC15 */
+	GPIO_DEFAULT,	/* S0_NC16 - XDP_GPIO_S0_NC16 */
+	GPIO_DEFAULT,	/* S0_NC17 - XDP_GPIO_S0_NC17 */
+	GPIO_DEFAULT,	/* S0_NC18 - XDP_GPIO_S0_NC18 */
+	GPIO_DEFAULT,	/* S0_NC19 - XDP_GPIO_S0_NC19 */
+	GPIO_DEFAULT,	/* S0_NC20 - XDP_GPIO_S0_NC20 */
+	GPIO_DEFAULT,	/* S0_NC21 - XDP_GPIO_S0_NC21 */
+	GPIO_DEFAULT,	/* S0_NC22 - XDP_GPIO_S0_NC22 */
+	GPIO_DEFAULT,	/* S0_NC23 - XDP_GPIO_S0_NC23 */
+	GPIO_NC,	/* S0_NC24 - NC */
+	GPIO_NC,	/* S0_NC25 - NC */
+	GPIO_NC,	/* S0_NC26 - NC */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_ACPI_SCI,	/* S0_SC000 - SOC_KBC_SCI - INT */
+	GPIO_FUNC2,	/* S0_SC001 - SATA_DEVSLP_C */
+	GPIO_NC,	/* S0-SC002 - SATA_LED_R_N (NC/PU) */
+	GPIO_FUNC1,	/* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+	GPIO_FUNC1,	/* S0-SC004 - PCIE_CLKREQ_WLAN# */
+	GPIO_NC,	/* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+	GPIO_NC,	/* S0-SC006 - PCIE_CLKREQ3# (NC) */
+	GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+	GPIO_NC,	/* S0-SC008 - ACZ_RST# (NC) */
+	GPIO_NC,	/* S0-SC009 - ACZ_SYNC (NC) */
+	GPIO_NC,	/* S0-SC010 - ACZ_BCLK (NC) */
+	GPIO_NC,	/* S0-SC011 - ACZ_STDOUT (NC) */
+	GPIO_NC,	/* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+	GPIO_NC,	/* S0-SC013 - NC */
+	GPIO_INPUT,	/* S0-SC014 - DET_TRIGGER - INT */
+	GPIO_INPUT,	/* S0-SC015 - AJACK_MICPRES_L - INT */
+	GPIO_FUNC(3, PULL_DOWN, 20K),	/* S0-SC016 - MMC1_45_CLK  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC017 - MMC1_45_D[0] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC018 - MMC1_45_D[1] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC019 - MMC1_45_D[2] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC020 - MMC1_45_D[3] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC021 - MMC1_45_D[4] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC022 - MMC1_45_D[5] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC023 - MMC1_45_D[6] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC024 - MMC1_45_D[7] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC025 - MMC1_45_CMD  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC026 - MMC1_45_RST  */
+	GPIO_NC,	/* S0-SC027 - NC */
+	GPIO_NC,	/* S0-SC028 - NC */
+	GPIO_NC,	/* S0-SC029 - NC */
+	GPIO_NC,	/* S0-SC030 - NC */
+	GPIO_NC,	/* S0-SC031 - NC */
+	GPIO_NC,	/* S0-SC032 - NC */
+	GPIO_FUNC(1, PULL_DOWN, 20K),	/* S0-SC033 - SD3_CLK */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC034 - SD3_D0 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC035 - SD3_D1 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC036 - SD3_D2 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC037 - SD3_D3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC038 - SD3_CD# */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC039 - SD3_CMD */
+	GPIO_NC,	/* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC041 - SDIO3_PWR_EN# */
+	GPIO_FUNC1,	/* S0-SC042 - LPC_LAD0 */
+	GPIO_FUNC1,	/* S0-SC043 - LPC-LAD1 */
+	GPIO_FUNC1,	/* S0-SC044 - LPC_LAD2 */
+	GPIO_FUNC1,	/* S0-SC045 - LPC_LAD3 */
+	GPIO_FUNC1,	/* S0-SC046 - LPC_LFRAME# */
+	GPIO_FUNC1,	/* S0-SC047 - PCLK_TPM */
+	GPIO_FUNC1,	/* S0-SC048 - CLK_PCI_EC */
+	GPIO_FUNC1,	/* S0-SC049 - LPC_CLKRUN_L */
+	GPIO_NC,	/* S0-SC050 - IRQ_SERIRQ */
+	GPIO_NC,	/* S0-SC051 - SMB_SOC_DATA (XDP) */
+	GPIO_NC,	/* S0-SC052 - SMB_SOC_CLK (XDP) */
+	GPIO_NC,	/* S0-SC053 - SMB_SOC_ALERTB (NC) */
+	GPIO_DEFAULT,	/* S0-SC054 - NC */
+	GPIO_DIRQ,	/* S0-SC055 - TRACKPAD_INT_DX */
+	GPIO_INPUT,	/* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+	GPIO_FUNC1,	/* S0-SC057 - PCH_UART_TXD */
+	GPIO_INPUT,	/* S0-SC058 - SIM_DET_C */
+	GPIO_INPUT_LEGACY,	/* S0-SC059 - EC_IN_RW_C */
+	GPIO_NC,	/* S0-SC060 - NC */
+	GPIO_FUNC1,	/* S0-SC061 - SOC_UART_RX */
+	GPIO_FUNC1,	/* S0-SC062 - I2S_BCLK */
+	GPIO_FUNC1,	/* S0-SC063 - I2S_LRCLK */
+	GPIO_FUNC1,	/* S0-SC064 - I2S_DIN */
+	GPIO_FUNC1,	/* S0-SC065 - I2S_DOUT */
+	GPIO_FUNC1,	/* S0-SC066 - SIO_SPI_CS# */
+	GPIO_FUNC1,	/* S0-SC067 - SIO_SPI_MISO */
+	GPIO_FUNC1,	/* S0-SC068 - SIO_SPI_MOSI */
+	GPIO_FUNC1,	/* S0-SC069 - SIO_SPI_CLK */
+	GPIO_DIRQ,	/* S0-SC070 - ALS_INT_L - INT */
+	GPIO_NC,	/* S0-SC071 - NC */
+	GPIO_DIRQ,	/* S0-SC072 - TOUCH_INT_L_DX */
+	GPIO_NC,	/* S0-SC073 - NC */
+	GPIO_NC,	/* S0-SC074 - SIO_UART2_RXD (NC) */
+	GPIO_NC,	/* S0-SC075 - SIO_UART2_TXD (NC) */
+	GPIO_INPUT,	/* S0-SC076 - BIOS_STRAP - STRAP */
+	GPIO_INPUT,	/* S0-SC077 - SOC_OVERRIDE - STRAP */
+	GPIO_FUNC1,	/* S0-SC078 - I2C_0_SDA */
+	GPIO_FUNC1,	/* S0-SC079 - I2C_0_SCL */
+	GPIO_FUNC1,	/* S0-SC080 - I2C_1_SDA */
+	GPIO_FUNC1,	/* S0-SC081 - I2C_1_SCL */
+	GPIO_NC,	/* S0-SC082 - NC */
+	GPIO_NC,	/* S0-SC083 - NC */
+	GPIO_NC,	/* S0-SC084 - NC */
+	GPIO_NC,	/* S0-SC085 - NC */
+	GPIO_FUNC1,	/* S0-SC086 - I2C_4_SDA */
+	GPIO_FUNC1,	/* S0-SC087 - I2C_4_SCL */
+	GPIO_NC,	/* S0-SC088 - I2C_5_SDA */
+	GPIO_NC,	/* S0-SC089 - I2C_5_SCL */
+	GPIO_NC,	/* S0-SC090 - NC */
+	GPIO_NC,	/* S0-SC091 - NC */
+	GPIO_NC,	/* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+	GPIO_NC,	/* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+	GPIO_NC,	/* S0-SC094 - NC */
+	GPIO_NC,	/* S0-SC095 - SIO_PWM1 (NC) */
+	GPIO_FUNC1,	/* S0-SC096 - I2S_MCLK */
+	GPIO_NC,	/* S0-SC097 - NC */
+	GPIO_NC,	/* S0-SC098 - NC */
+	GPIO_NC,	/* S0-SC099 - NC */
+	GPIO_NC,	/* S0-SC100 - NC */
+	GPIO_DIRQ,	/* S0-SC101 - KBD_IRQ# */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_ACPI_WAKE,	/* S500 - PCH_WAKE# */
+	GPIO_ACPI_WAKE,	/* S501 - TRACKPAD_INT# - INT */
+	GPIO_ACPI_WAKE,	/* S502 - TOUCH_INT# - INT */
+	GPIO_FUNC(6, PULL_UP, 20K),	/* S503 - LTE_WAKE_L# - INT */
+	GPIO_NC,	/* S504 - SOC_JTAG2_TDO (NC/PU) */
+	GPIO_FUNC1,	/* S505 - SUS_CLK_WLAN (NC) */
+	GPIO_INPUT_PU,	/* S506 - PCH_SPI_WP */
+	GPIO_ACPI_SMI,	/* S507 - SOC_KBC_SMI - INT */
+	GPIO_NC,	/* S508 - NC */
+	GPIO_DIRQ,	/* S509 - MUX_AUD_INT1# */
+	GPIO_OUT_HIGH,	/* S510 - WIFI_DISABLE_L */
+	GPIO_FUNC0,	/* S511 - SUSPWRDNACK */
+	GPIO_FUNC0,	/* S512 - WIFI_SUSCLK */
+	GPIO_FUNC0,	/* S513 - SLP_SX */
+	GPIO_NC,	/* S514 - NC */
+	GPIO_FUNC0,	/* S515 - WLAN_WAKE_L - INT */
+	GPIO_FUNC0,	/* S516 - PCH_PWRBTN_L */
+	GPIO_NC,	/* S517 - NC */
+	GPIO_FUNC0,	/* S518 - SUS_STAT# */
+	GPIO_FUNC0,	/* S519 - USB_OC0# */
+	GPIO_FUNC0,	/* S520 - USB_OC1# */
+	GPIO_NC,	/* S521 - NC */
+	GPIO_NC,	/* S522 - XDP_GPIO_DFX0 */
+	GPIO_NC,	/* S523 - XDP_GPIO_DFX1 */
+	GPIO_NC,	/* S524 - XDP_GPIO_DFX2 */
+	GPIO_NC,	/* S525 - XDP_GPIO_DFX3 */
+	GPIO_NC,	/* S526 - XDP_GPIO_DFX4 */
+	GPIO_NC,	/* S527 - XDP_GPIO_DFX5 */
+	GPIO_NC,	/* S528 - XDP_GPIO_DFX6 */
+	GPIO_NC,	/* S529 - XDP_GPIO_DFX7 */
+	GPIO_NC,	/* S530 - XDP_GPIO_DFX8 */
+	GPIO_NC,	/* S531 - NC */
+	GPIO_NC,	/* S532 - NC */
+	GPIO_NC,	/* S533 - NC */
+	GPIO_NC,	/* S534 - NC */
+	GPIO_OUT_HIGH,	/* S535 - LTE_DISABLE_L */
+	GPIO_NC,	/* S536 - NC */
+	GPIO_INPUT,	/* S537 - RAM_ID0 */
+	GPIO_INPUT,	/* S538 - RAM_ID1 */
+	GPIO_INPUT,	/* S539 - RAM_ID2 */
+	GPIO_NC,	/* S540 - NC */
+	GPIO_NC,	/* S541 - NC */
+	GPIO_NC,	/* S542 - NC */
+	GPIO_NC,	/* S543 - NC */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+	[TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+	[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+	[ALS_IRQ_OFFSET] = ALS_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000000..e9b78a864f
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/dptf.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	80
+#define DPTF_CPU_CRITICAL	90
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	48
+#define DPTF_TSR0_CRITICAL	70
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	60
+#define DPTF_TSR1_CRITICAL	70
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	55
+#define DPTF_TSR2_CRITICAL	70
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 },	/* 0.128A */
+})
diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000000..772b4bac06
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl
@@ -0,0 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <variant/onboard.h>
+
+/* Elan trackpad */
+#include <mainboard/google/rambi/acpi/trackpad_elan.asl>
diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h b/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h
new file mode 100644
index 0000000000..1477794851
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/rambi/irqroute.h>
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO             ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TRACKPAD_NAME             "trackpad"
+#define BOARD_TRACKPAD_IRQ              GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO        ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS          0
+#define BOARD_TRACKPAD_I2C_ADDR         0x15
+
+#define BOARD_I8042_IRQ                 GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+#define BOARD_ALS_IRQ                   GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET)
+
+#define BOARD_ALS_I2C_ADDR         	0x44
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h b/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h
new file mode 100644
index 0000000000..08e75636d2
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_H
+#define VARIANT_H
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+ * 0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz
+ * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b101 - 2GiB total - 2 x 1GiB Samsung K4B2G1646Q-BYK0 1600MHz
+ * 0b110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ */
+
+static const uint32_t dual_channel_config =
+	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+
+#endif