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authorAaron Durbin <adurbin@chromium.org>2016-07-25 21:31:41 -0500
committerDuncan Laurie <dlaurie@chromium.org>2016-07-30 01:36:32 +0200
commitb0f81518b5c17466bc95ebdef292e82c4b76bc88 (patch)
tree7174d0006c9a8450ada5aeb7c6fe6377407e96a6 /src/mainboard/google/rambi/acpi/chromeos.asl
parent212820c8d728c59fa3228ce92bc1d549b232e35a (diff)
chromeos mainboards: remove chromeos.asl
Use the ACPI generator for creating the Chrome OS gpio package. Each mainboard has its own list of Chrome OS gpios that are fed into a helper to generate the ACPI external OIPG package. Additionally, the common chromeos.asl is now conditionally included based on CONFIG_CHROMEOS. Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google/rambi/acpi/chromeos.asl')
-rw-r--r--src/mainboard/google/rambi/acpi/chromeos.asl32
1 files changed, 0 insertions, 32 deletions
diff --git a/src/mainboard/google/rambi/acpi/chromeos.asl b/src/mainboard/google/rambi/acpi/chromeos.asl
deleted file mode 100644
index 3072ecaaa6..0000000000
--- a/src/mainboard/google/rambi/acpi/chromeos.asl
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * Fields are in the following order.
- * - Type: recovery = 1 developer mode = 2 write protect = 3
- * - Active Level - if -1 not a valid gpio
- * - GPIO number encoding - if -1 not a valid gpio
- * - Chipset Name
- *
- * Note: On Bay Trail we need to encode gpios within the 3 separate banks
- * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded
- * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000.
- */
-
-Name(OIPG, Package() {
- // No physical recovery button
- Package () { 0x0001, 0, 0xFFFFFFFF, "BayTrail" },
- Package () { 0x0003, 1, 0x2006, "BayTrail" },
-})