diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-01-17 21:51:07 +0100 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-02-08 23:15:48 +0000 |
| commit | d571ea2eac6e9c1891b1b3fe0536c3319786ba48 (patch) | |
| tree | f692540299e321d7fac01c8291f5e5e02d9e962b /src/mainboard/google/puff/variants/wyvern/overridetree.cb | |
| parent | e04ee222d5f302497b2023eedf29b1d728aead51 (diff) | |
mb/google/puff: Use chipset dt reference names
Use the references from the chipset devicetree as this makes the
comments superfluous.
Change-Id: I06a3acca0a72ff158a0143acc87d9479b2deb0d5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/google/puff/variants/wyvern/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/puff/variants/wyvern/overridetree.cb | 44 |
1 files changed, 24 insertions, 20 deletions
diff --git a/src/mainboard/google/puff/variants/wyvern/overridetree.cb b/src/mainboard/google/puff/variants/wyvern/overridetree.cb index 60ba0bcf51..715ef7ffba 100644 --- a/src/mainboard/google/puff/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/puff/variants/wyvern/overridetree.cb @@ -203,7 +203,7 @@ chip soc/intel/cannonlake register "sata_port[1].TxGen3DeEmph" = "0x20" device domain 0 on - device pci 04.0 on + device ref dptf on chip drivers/intel/dptf ## Active Policy register "policies.active[0]" = "{.target=DPTF_CPU, @@ -267,8 +267,8 @@ chip soc/intel/cannonlake device generic 0 on end end - end # DPTF 0x1903 - device pci 14.0 on + end + device ref xhci on chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi @@ -348,29 +348,31 @@ chip soc/intel/cannonlake end end end - end # USB xHCI - device pci 15.0 off + end + device ref i2c0 off # RFU - Reserved for Future Use. - end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 on + end + device ref i2c1 off end + device ref i2c2 on + # PCON PS175 chip drivers/i2c/generic register "hid" = ""1AF80175"" register "name" = ""PS17"" register "desc" = ""Parade PS175"" device i2c 4a on end end - end # I2C #2, PCON PS175. - device pci 15.3 on + end + device ref i2c3 on + # Realtek RTD2142 chip drivers/i2c/generic register "hid" = ""10EC2142"" register "name" = ""RTD2"" register "desc" = ""Realtek RTD2142"" device i2c 4a on end end - end # I2C #3, Realtek RTD2142. - device pci 16.0 on end # Management Engine Interface 1 - device pci 19.0 on + end + device ref heci1 on end + device ref i2c4 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -383,22 +385,24 @@ chip soc/intel/cannonlake register "property_list[0].integer" = "1" device i2c 1a on end end - end #I2C #4 - device pci 1a.0 on end # eMMC - device pci 1c.6 on + end + device ref emmc on end + device ref pcie_rp7 on + # RTL8111H Ethernet NIC chip drivers/net register "customized_leds" = "0x05af" register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device ref system_agent on end end register "PcieRpSlotImplemented[6]" = "1" - end # RTL8111H Ethernet NIC - device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + end + device ref pcie_rp11 on + # X2 NVMe register "PcieRpSlotImplemented[10]" = "1" end - device pci 1e.3 off end # GSPI #1 + device ref gspi1 off end end # VR Settings Configuration for 4 Domains |