diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2024-01-21 20:48:26 -0600 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-02-08 23:16:22 +0000 |
| commit | 8facfa84acee18b069a6a6b53491358a7ad1017e (patch) | |
| tree | d235c2ad02298dc8d1d2233ce6a370ed19af2be4 /src/mainboard/google/puff/variants/moonbuggy/overridetree.cb | |
| parent | 3f4c830bf64ac8a0761729f831d51f0a1d6c89f4 (diff) | |
mb/google/puff/var/*: Clean up SerialIO/I2C config in overridetree
Ensure that the SerialIoDevMode config and common_soc_config registers
for each variant are programmed consistently with the devices'
enabled status in that variant's overridetree; remove and disable
extraneous devices as appropriate.
TEST=build/boot several puff variants, verify all components working
as expected, nothing missing from cbmem, lspci, etc.
Change-Id: Ib9d0cf48e405be7c00c553646651fc6f28c4e3f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80164
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/puff/variants/moonbuggy/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/puff/variants/moonbuggy/overridetree.cb | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb index 4fb617b047..aa2377e878 100644 --- a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb +++ b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb @@ -8,9 +8,9 @@ chip soc/intel/cannonlake [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoDisabled, [PchSerialIoIndexSPI2] = PchSerialIoDisabled, [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoPci, @@ -150,7 +150,6 @@ chip soc/intel/cannonlake #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | - #| I2C0 | RFU | #| I2C2 | PS175 | #| I2C3 | MST | #| I2C4 | Audio | @@ -160,11 +159,6 @@ chip soc/intel/cannonlake .speed_mhz = 1, .early_init = 1, }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 0, - .fall_time_ns = 0, - }, .i2c[2] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 60, |